Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
AssigneeAtomera Incorporated
InventorsRobert J. Mears, Hideki Takeuchi
Life of this patent
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Abstract
A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.
Claims21
A semiconductor device comprising:
- a semiconductor substrate;
- and
- a plurality of field effect transistors (FETs) on the semiconductor substrate and each comprising
- a gate,
- spaced apart source and drain regions on opposite sides of the gate,
- upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
- a halo implant having a peak halo dopant concentration of at least 1×1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
- a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×1019 atoms/cm3.
A semiconductor device comprising:
- a semiconductor substrate;
- and
- a plurality of CMOS transistors on the semiconductor substrate and each comprising
- a gate,
- spaced apart source and drain regions on opposite sides of the gate,
- upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
- a halo implant having a peak halo dopant concentration of at least 1×1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
- a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×1019 atoms/cm3;
- the upper and lower superlattice layers each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
A method of making a semiconductor device comprising:
- forming a plurality of field effect transistors (FETs) on a semiconductor substrate, each comprising
- a gate,
- spaced apart source and drain regions on opposite sides of the gate,
- upper and lower vertically stacked superlattice layers and a first bulk semiconductor layer therebetween between the source and drain regions,
- a halo implant having a peak halo dopant concentration of at least 1×1019 atoms/cm3 vertically confined in the first bulk semiconductor layer between the upper and lower superlattice layers, and
- a second bulk semiconductor layer on the upper superlattice layer defining a channel region and having a concentration of the halo dopant less than 1×1019 atoms/cm3.
Dependencies are inferred from the claim text.