Non-volatile memory device having nanocrystal floating gate and method of fabricating same

A method for fabricating a non-volatile memory device, the method comprising:

• forming a semiconductor layer stack over a substrate, wherein the semiconductor layer stack includes at least one first semiconductor layer of a first semiconductor material and at least one second semiconductor layer of a second semiconductor material, the second semiconductor material being different than the first semiconductor material;
• forming a gate structure over a channel region of the semiconductor layer stack, wherein the gate structure includes a dummy gate stack, sacrificial gate spacers, and gate spacers;
• removing the sacrificial gate spacers to form a first opening in the gate structure that exposes a first portion of the semiconductor layer stack in the channel region;
• removing a portion of the at least one second semiconductor layer from the exposed first portion of the semiconductor layer stack;
• removing the dummy gate stack to form a second opening in the gate structure that exposes a second portion of the semiconductor layer stack in the channel region, wherein the exposed second portion includes at least one second semiconductor layer island;
• forming an oxide layer over the at least one second semiconductor layer island;
• and
• forming a metal gate stack in the second opening of the gate structure.

A method for fabricating a non-volatile memory device, the method comprising:

• forming a fin structure over a substrate, wherein the fin structure includes at least one first semiconductor layer of a first semiconductor material and at least one second semiconductor layer of a second semiconductor material, the second semiconductor material being different than the first semiconductor material;
• forming a gate structure that includes a dummy gate over a portion of the fin structure, the gate structure traversing the fin structure, such that the gate structure separates a source region and a drain region of the fin structure, a channel region being defined between the source region and the drain region;
• and
• during a gate replacement process for replacing the dummy gate with a control gate over the channel region, forming a nanowire in the channel region from the first semiconductor layer and a nanocrystal floating gate in the channel region from the second semiconductor layer.