Phase continuity technique for frequency synthesis
AssigneeQUALCOMM Incorporated
InventorsMarco Zanuso, Mohammad Elbadry, Tsai-Pi Hung, Ravi Sridhara, Francesco Gatta, Jingcheng Zhuang
Life of this patent
Estimating the term…
Abstract
A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
Claims17
A method of wireless communication, comprising:
- powering down a first phase lock loop during a transmit subframe in time division duplex (TDD) communications;
- clocking at least a portion of a delta sigma modulator with a reference clock for the first phase lock loop when the first phase lock loop powers down;
- and
- maintaining phase continuity when the first phase lock loop turns back on.
A method of wireless communication, comprising:
- changing a frequency of a phase lock loop from a first frequency to a second frequency;
- switching between a first delta sigma modulator and a second delta sigma modulator when the frequency of the phase lock loop changes, while maintaining power on both the first delta sigma modulator and a clock of the first delta sigma modulator;
- and
- maintaining phase continuity when the phase lock loop returns to the first frequency.
An apparatus comprising:
- a first phase lock loop including a delta sigma modulator;
- a second phase lock loop, the first phase lock loop and the second phase lock loop associated with frequency division duplex (FDD) communications;
- a control unit coupled to the first phase lock loop, the control unit configured to cause the first phase lock loop to power down;
- and
- a reference clock device coupled to the delta sigma modulator, the reference clock device configured to generate a reference clock signal to clock at least a portion of the delta sigma modulator with the reference clock signal when the first phase lock loop powers down, the control unit configured to maintain phase continuity when the first phase lock loop turns back on based at least in part on the clocking, in which the control unit causes the first phase lock loop to power down during sleep mode while the delta sigma modulator and the reference clock of the first phase lock loop stay active to maintain phase continuity.
An apparatus comprising:
- a control unit coupled to a phase lock loop;
- a first delta sigma modulator coupled to the phase lock loop;
- and
- a second delta sigma modulator coupled to the phase lock loop, the control unit configured to change a frequency of the phase lock loop from a first frequency to a second frequency, the control unit configured to cause a switch between the first delta sigma modulator and the second delta sigma modulator when the frequency of the phase lock loop changes, while maintaining power on both the first delta sigma modulator and a clock of the first delta sigma modulator, the control unit configured to maintain phase continuity when the phase lock loop returns to the first frequency based at least in part on the maintaining of the power on both the first delta sigma modulator and the clock of the first delta sigma modulator.
Dependencies are inferred from the claim text.