US 9,893,728 B2Granted

Wideband highly-linear low output impedance D2S buffer circuit

AssigneeMediatek Inc.

InventorsFei Song, Osama Shana'a, Yuen Hui Chee

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Abstract

A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Claims18

Dependent claims

A circuit comprising:

a first signal transistor having a first terminal, a control terminal, and a second terminal;
a current source having a first terminal and a second terminal, wherein the first terminal of the current source is coupled to the first terminal of the first signal transistor, and wherein the second terminal of the current source is coupled to the control terminal of the first signal transistor;
a second signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the second signal transistor is coupled to the second terminal of the current source, and wherein the first terminal of the second signal transistor is coupled to the second terminal of the first signal transistor;
a third signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the third signal transistor is coupled to the first terminal of the second signal transistor;
a buffer input;
a first bias circuit that AC couples the buffer input to the control terminal of the second signal transistor;
a second bias circuit that AC couples the second terminal of the second signal transistor to the control terminal of the third signal transistor;
a double-ended to single-ended (D2S) circuit having an D2S output lead, wherein the D2S output lead is coupled to the buffer input;
a receive chain comprising a Low Noise Amplifier (LNA), a mixer, and a base band filter, wherein the buffer output is coupled to inject a signal into the receive chain;
a transmit chain comprising a base band filter, a mixer, and a Power Amplifier (PA), wherein the PA is coupled to the buffer input such that a differential signal output by the PA is supplied in attenuated form to the D2S circuit;
and
a buffer output that is coupled to the first terminal of the second signal transistor.

9 more elements

A circuit comprising:

a first signal transistor having a first terminal, a control terminal, and a second terminal;
a current source having a first terminal and a second terminal, wherein the first terminal of the current source is coupled to the first terminal of the first signal transistor, and wherein the second terminal of the current source is coupled to the control terminal of the first signal transistor;
a second signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the second signal transistor is coupled to the second terminal of the current source, and wherein the first terminal of the second signal transistor is coupled to the second terminal of the first signal transistor;
a third signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the third signal transistor is coupled to the first terminal of the second signal transistor;
a first buffer input;
a first bias circuit that AC couples the first buffer input to the control terminal of the second signal transistor;
a second buffer input;
a second bias circuit that AC couples the second buffer input to the control terminal of the third signal transistor;
and
a buffer output that is coupled to the first terminal of the second signal transistor.

7 more elements

A circuit comprising:

a first signal transistor having a first terminal, a control terminal, and a second terminal;
a second signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the second signal transistor is coupled to the control terminal of the first signal transistor, and wherein the first terminal of the second signal transistor is coupled to the second terminal of the first signal transistor;
a third signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the third signal transistor is coupled to the first terminal of the second signal transistor;
a fourth signal transistor having a first terminal, a control terminal, and a second terminal, wherein the second terminal of the fourth signal transistor is coupled to the second terminal of the second signal transistor, and wherein the first terminal of the fourth signal transistor is coupled to the first terminal of the first signal transistor;
a first buffer input;
a first bias circuit that AC couples the first buffer input to the control terminal of the second signal transistor;
a second buffer input;
a second bias circuit that AC couples the second buffer input to the control terminal of the third signal transistor;
a third bias circuit that AC couples the first buffer input to the control terminal of the fourth signal transistor;
and
a buffer output that is coupled to the first terminal of the second signal transistor.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/862,520Filed 23 Sep 2015 · us provisional application
Priority: 9 Jun 2015
Published: US 2016/0365859 A115 Dec 2016
Granted: 13 Feb 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification30 codes

H03K 19/018514
Interface arrangements: with at least one differential stage
H03F 3/195
With semiconductor devices only: in integrated circuits
H03F 3/3028
CMOS common source output SEPP amplifiers: with symmetrical driving of the end stage
H03F 3/3033
With field-effect transistors: nMOS SEPP output stages