US 9,893,004 B2Granted

Semiconductor interposer integration

AssigneeBroadPak Corporation

InventorFarhang Yazdani

Life of this patent

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Abstract

Integrated circuits are described which directly connect a semiconductor interposer to a motherboard or printed circuit board by way of large pitch connections. A stack of semiconductor interposers may be connected directly to one another by a variety of means and connected to a printed circuit board through only a ball grid array of solder bumps. The stack of semiconductor interposers may include one or more semiconductor interposers which are shifted laterally to enable directly electrical connections to intermediate semiconductor interposers. The top semiconductor interposer may have no electrical connections on the top to increase security by making electrical “taps” much more difficult. An electrically insulating layer may be incorporated between adjacent semiconductor interposers and cavities or air gaps may also be included within one or more semiconductor interposers.

Claims14

Dependent claims

An integrated circuit package comprising:

a first semiconductor interposer comprising a first plurality of through vias substantially perpendicular to a major plane of the first semiconductor interposer and extending through an entire thickness of the first semiconductor interposer;
and
a second semiconductor interposer positioned below said first semiconductor interposer, said second interposer comprising a second plurality of through vias substantially perpendicular to a major plane of the second semiconductor interposer and extending through an entire thickness of the second semiconductor interposer, wherein
the entire surface of a lower semiconductor surface of the first semiconductor interposer is directly connected to an upper surface of a silicon oxide layer and a bottom surface of the silicon oxide layer is directly connected to the entire surface of an upper semiconductor surface of the second semiconductor interposer, and
electrical signals are transmitted through the silicon oxide layer inductively or capacitively between the first semiconductor interposer and the second semiconductor interposer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/717,798Filed 20 May 2015 · continuation in part
Priority: 27 Jul 2011
Published: US 2015/0255434 A110 Sep 2015
Granted: 13 Feb 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10W 70/635
Vias, e.g. via plugs: through-vias
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 40/47
Involving heat exchange by flowing fluids: by flowing liquids, e.g. forced water cooling
H10W 42/40
Arrangements for protection of devices: protecting against tampering, e.g. unauthorised inspection or reverse engineering

Family

Application13/192,217Parent of this continuation-in-part · filed 27 Jul 2011
Application62/002,794Us provisional application · filed 24 May 2014
US 2015/0255434 A1Pre-grant publication · published 10 Sep 2015
US 10,236,275 B2Related patent
US 2011/0278737 A1Published application
US 9,893,004 B2This patent

From the US filing history. Foreign family members aren’t listed.