Timing controller, display system including the same, and method of use thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJae Chul Lee, Jong Seon Kim, Yun Hee Kang, Hyun Je Park, Myung Seok Oh, Se Moon Oh
Life of this patent
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Abstract
A timing controller capable of communicating with a host via a Mobile Industry Processor Interface (MIPI) interface and communicating with a display via a display interface, includes a detection circuit that detects whether at least one of the MIPI interface and the timing controller is operating normally, and generates a detection signal, and an interrupt generation circuit that transmits the detection signal as an interrupt to the host via an exclusive line.
Claims20
A timing controller capable of communicating with a host via a Mobile Industry Processor Interface (MIPI) interface and communicating with a display via a display interface, the timing controller comprising:
- a detection circuit that detects whether at least one of the MIPI interface and the timing controller is operating normally, and generates a detection signal;
- an interrupt generation circuit that transmits the detection signal as an interrupt to the host via an exclusive line;
- and
- a clock lane module,
- wherein the detection circuit detects a transition of an operation mode of the timing controller from a low power (LP) mode to a high speed (HS) mode based on an output signal of the clock lane module, and outputs the detection signal, and the clock lane module maintains the HS mode in response to the detection signal even when the output signal of the clock lane module is changed by external noise in the HS mode.
A display system comprising:
- a host;
- a timing controller that communicates with the host via a Mobile Industry Processor Interface (MIPI) interface;
- and
- a display that communicates with the timing controller via a display interface,
- wherein the timing controller comprises:
- a detection circuit that detects whether at least one of the MIPI interface and the timing controller is operating normally, and generates a detection signal;
- and
- an interrupt generation circuit that transmits the detection signal as an interrupt to the host via an exclusive line,
- wherein the timing controller further comprises a clock lane module,
- the detection circuit detects a transition of an operation mode of the timing controller from a low power (LP) mode to a high speed (HS) mode based on an output signal of the clock lane module, and outputs the detection signal, and
- the clock lane module maintains the HS mode in response to the detection signal even when the output signal of the clock lane module is changed by external noise in the HS mode.
Dependencies are inferred from the claim text.