US 9,887,206 B2Granted

Method of making split gate non-volatile memory cell with 3D FinFET structure

AssigneeSilicon Storage Technology, Inc.

InventorsChien-Sheng Su, Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Hieu Van Tran, Nhan Do

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Abstract

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

A method of forming a non-volatile memory cell, comprising:

forming a pair of parallel trenches into a surface of a semiconductor substrate of a first conductivity type, resulting in a fin shaped upper surface portion between the trenches having a top surface and two side surfaces;
forming insulation material along the top surface and the two side surfaces;
forming spaced apart first and second regions of a second conductivity type different than the first conductivity type in the fin shaped upper surface portion, with a channel region extending between the first region and the second region;
wherein the channel region has a first portion that includes a first portion of the top surface and first portions of the two side surfaces, and has a second portion that includes a second portion of the top surface and second portions of the two side surfaces,
forming a conductive floating gate that includes:
a first portion that extends along and is insulated from the first portion of the top surface,
a second portion that extends along and is insulated from the first portion of one of the two side surfaces, and
a third portion that extends along and is insulated from the first portion of the other of the two side surfaces;
forming a conductive control gate that includes:
a first portion that extends along and is insulated from the second portion of the top surface,
a second portion that extends along and is insulated from the second portion of one of the two side surfaces,
a third portion that extends along and is insulated from the second portion of the other of the two side surfaces,
a fourth portion that extends up and over and is insulated from at least some of the floating gate first portion,
a fifth portion that extends out and over and is insulated from at least some of the floating gate second portion, and
a sixth portion that extends out and over and is insulated from at least some of the floating gate third portion.

12 more elements

Facts

Application

15/453,829Filed 8 Mar 2017 · division

Priority

17 Mar 2015

Published

US 2017/0179141 A122 Jun 2017

Granted

6 Feb 2018

Term ends

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Classification13 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/20
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by three-dimensional [3D] arrangements, e.g.…
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/0245
Of fin field-effect transistors [FinFET]: by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins

Family

Application62/134,489Us provisional application · filed 17 Mar 2015

Application15/050,309Parent of this division · filed 22 Feb 2016

US 2017/0179141 A1Pre-grant publication · published 22 Jun 2017

US 9,634,018 B2Parent of this division

US 2016/0276357 A1Published application

US 9,887,206 B2This patent

From the US filing history. Foreign family members aren’t listed.

Abstract

Claims5