# US 9,883,595 B2 · Substrate structures and methods of manufacture

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- Number: US 9,883,595 B2
- Document ID: US9883595B2
- Status: Granted
- Kind: B2
- Application number: 15/206,574
- Filed: 2016-07-11
- Published: 2016-11-03
- Granted: 2018-01-30
- Earliest claimed: 2014-11-06
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Yusheng Lin; Sadamichi Takakusaki
- Web page: https://patentgrep.com/patent/US9883595B2

## CPC

- H05K 3/06: the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)}
- C04B 37/021: {in a direct manner, e.g. direct copper bonding [DCB]}
- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 1/0313: {Organic insulating material}
- H05K 1/036: {Multilayers with layers of different types}
- H05K 1/056: {the metal substrate being covered by an organic insulating layer}
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 3/0011: {Working of insulating substrates or insulating layers}
- H05K 3/064: {Photoresists}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/6875: {being on a metallic substrate, e.g. insulated metal substrates [IMS]}
- H10W 70/692: Ceramics or glasses
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- C04B 2237/34: Oxidic
- C04B 2237/343: Alumina or aluminates
- C04B 2237/402: Aluminium
- C04B 2237/406: Iron, e.g. steel
- C04B 2237/407: Copper
- C04B 2237/52: Pre-treatment of the joining surfaces, e.g. cleaning, machining
- C04B 2237/64: Forming laminates or joined articles comprising grooves or cuts
- C04B 2237/82: Two substrates not completely covering each other, e.g. two plates in a staggered position
- H05K 3/0058: {Laminating printed circuit boards onto other substrates, e.g. metallic substrates (H05K1/0281 takes precedence)}
- H05K 3/0064: {onto a polymeric substrate}
- H05K 3/0067: {onto an inorganic, non-metallic substrate}
- H05K 3/20: by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)}
- H05K 3/202: {using self-supporting metal foil pattern}
- H05K 2201/09736: Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
- H10W 70/685: comprising multiple insulating layers
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

## Claims

### Claim 1

A method of forming an insulated metal substrate (IMS) for a power electronic, comprising:
partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface of the copper layer opposite the first surface of the copper layer;
laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and
forming traces in the copper layer by etching through the copper layer at the first thickness and etching completely through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the pattern further comprises forming a third thickness different in magnitude from the first thickness and the second thickness, the third thickness measured perpendicular to the first surface of the dielectric layer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising plating a layer of nickel onto the second surface of the copper layer, and wherein forming the traces in the copper layer further comprises etching through the layer of nickel.

### Claim 4 (depends on 1)

The method of claim 1, wherein etching through the copper layer at the first thickness and etching through the copper layer at the second thickness comprises coupling a first layer of photoresist to the second surface of the copper layer, forming a pattern in the first layer of photoresist, etching through the copper layer at the first thickness at spaces in the pattern in the first layer of photoresist, removing the first layer of photoresist, coupling a second layer of photoresist to the second surface of the copper layer, forming a pattern in the second layer of photoresist, etching through the copper layer at the second thickness at the spaces in the pattern in the second layer of photoresist, and removing the second layer of photoresist.

### Claim 5 (depends on 1)

The method of claim 1, further comprising laminating the traces in the copper layer with a second dielectric layer, coupling a second copper layer to the second dielectric layer, and forming traces in the second copper layer to form a stacked IMS for a power electronic.