# US 9,883,579 B1 · Package structure and manufacturing method thereof

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- Number: US 9,883,579 B1
- Document ID: US9883579B1
- Status: Granted
- Kind: B1
- Application number: 15/353,726
- Filed: 2016-11-16
- Granted: 2018-01-30
- Earliest claimed: 2016-10-07
- Assignees: Unimicron Technology Corp.
- Applicants: Unimicron Technology Corp.
- Inventors: Hsiang-Hung Huang
- Web page: https://patentgrep.com/patent/US9883579B1

## CPC

- H05K 1/0203: {Cooling of mounted components (H05K1/0272 takes precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via}
- H05K 1/182: associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 3/30: Assembling printed circuits with electric components, e.g. with resistors
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/4084: {by deforming at least one of the conductive layers}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H05K 2201/10083: Electromechanical or electro-acoustic component, e.g. microphone
- H05K 2201/10734: Ball grid array [BGA]; Bump grid array
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a circuit substrate, first and second build-up circuit structures, and a plurality of piezoelectric heat dissipation units. The circuit substrate includes a core layer, a plurality of electronic devices, and a conducting unit. The electronic devices are embedded in the core layer, and active surfaces of the two adjacent electronic devices respectively face a first surface and a second surface of the core layer. The conducting unit is disposed on the core layer and electrically connected to the electronic devices. The first and second build-up circuit structures are respectively disposed on the first and the second surfaces and respectively have at least one first and at least one second openings. The piezoelectric heat dissipation units respectively correspond to the active surfaces of the electronic devices and are electrically connected to the conducting unit exposed by the first and the second openings.

## Claims

### Claim 1

A package structure, comprising:
a circuit substrate, comprising:
a core layer having a first surface and a second surface opposite to each other;
a plurality of electronic devices embedded in the core layer, wherein each of the electronic devices has an active surface and a back surface opposite to each other, and the active surfaces of two adjacent electronic devices respectively face the first surface and the second surface of the core layer; and
a conducting unit disposed on the first surface and the second surface of the core layer and extended to the electronic devices and electrically connected to the electronic devices;
a first build-up circuit structure disposed on the first surface of the core layer and having at least one first opening;
a second build-up circuit structure disposed on the second surface of the core layer and having at least one second opening, wherein the first opening and the second opening expose a portion of the conducting unit; and
a plurality of piezoelectric heat dissipation units disposed on the conducting unit exposed by the first opening and the second opening and respectively corresponding to the active surfaces of the electronic devices, wherein the piezoelectric heat dissipation units are electrically connected to the conducting unit exposed by the first opening and the second opening.

### Claim 2 (depends on 1)

The package structure as recited in claim 1, wherein the core layer comprises a dielectric layer and an insulating layer, the dielectric layer has an upper surface and a lower surface opposite to each other and a plurality of holes, the electronic devices are respectively disposed in the holes, and the insulating layer covers the upper surface and the lower surface of the dielectric layer and is filled in the holes to cover the electronic devices.

### Claim 3 (depends on 1)

The package structure as recited in claim 1, wherein the conducting unit comprises:
a plurality of through-holes extended from the first surface and the second surface of the core layer to the electronic devices and electrically connected to the electronic devices;
a plurality of first pads disposed on the first surface and the second surface of the core layer, wherein the first pads are electrically connected to the active surfaces of the electronic devices via a portion of the through-holes;
a plurality of second pads disposed on the first surface and the second surface of the core layer and surrounding the first pads; and
a plurality of third pads disposed on the first surface and the second surface of the core layer, wherein the third pads are electrically connected to the back surfaces of the electronic devices via another portion of the through-holes.

### Claim 4 (depends on 3)

The package structure as recited in claim 3, wherein the first opening and the second opening expose the first pads and the second pads and the piezoelectric heat dissipation units are electrically connected to the first pads.

### Claim 5 (depends on 4)

The package structure as recited in claim 4, wherein each of the piezoelectric heat dissipation units comprises:
an elastic sheet;
a piezoelectric block disposed on the elastic sheet;
a first adhesive layer disposed on the piezoelectric block;
a buffer layer disposed on the first adhesive layer;
a second adhesive layer disposed on the buffer layer; and
two electrode wires embedded in the second adhesive layer, the buffer layer, and the first adhesive layer, wherein each of the electrode wires has a first end and a second end opposite to each other, the first end is embedded in a surface of the second adhesive layer relatively far from the buffer layer and in direct contact with one of the first pads, and the second end is in direct contact with the piezoelectric block.

### Claim 6 (depends on 3)

The package structure as recited in claim 3, wherein the first build-up circuit structure comprises a first dielectric layer and a plurality of first conductive vias, the first conductive vias pass through the first dielectric layer and are extended and disposed on a top surface of the first dielectric layer, and the first conductive vias are at least electrically connected to the third pads.

### Claim 7 (depends on 3)

The package structure as recited in claim 3, wherein the second build-up circuit structure comprises a second dielectric layer and a plurality of second conductive vias, the second conductive vias pass through the second dielectric layer and are extended and disposed on a bottom surface of the second dielectric layer, and the second conductive vias are at least electrically connected to the third pads.

### Claim 8 (depends on 1)

The package structure as recited in claim 1, wherein the circuit substrate further comprises:
a plurality of conductive columns passing through the core layer and extended and disposed on the first surface and the second surface of the core layer.

### Claim 9 (depends on 1)

The package structure as recited in claim 1, further comprising:
a third build-up circuit structure covering the first build-up circuit structure and having a plurality of first heat dissipation holes, wherein the first heat dissipation holes are disposed corresponding to the first opening; and
a fourth build-up circuit structure covering the second build-up circuit structure and having a plurality of second heat dissipation holes, wherein the second heat dissipation holes are disposed corresponding to the second opening.

### Claim 10 (depends on 9)

The package structure as recited in claim 9, wherein the fourth build-up circuit structure comprises a build-up dielectric layer and a plurality of build-up conductive vias, the build-up dielectric layer covers the second build-up circuit structure, the build-up conductive vias pass through the build-up dielectric layer and are extended and disposed on an outer surface of the build-up dielectric layer, and the build-up conductive vias are at least electrically connected to the second conductive vias.

### Claim 11

A manufacturing method of a package structure, comprising:
providing a circuit substrate, the circuit substrate comprising:
a core layer having a first surface and a second surface opposite to each other;
a plurality of electronic devices embedded in the core layer, wherein each of the electronic devices has an active surface and a back surface opposite to each other, and the active surfaces of two adjacent electronic devices respectively face the first surface and the second surface of the core layer; and
a conducting unit disposed on the first surface and the second surface of the core layer and extended to the electronic devices and electrically connected to the electronic devices;
respectively forming a first build-up circuit structure and a second build-up circuit structure on the first surface and the second surface of the core layer, wherein at least one first opening and at least one second opening are respectively formed in the first build-up circuit structure and the second build-up circuit structure, and the first opening and the second opening respectively expose a portion of the conducting unit; and
disposing a plurality of piezoelectric heat dissipation units on the conducting unit exposed by the first opening and the second opening, wherein the piezoelectric heat dissipation units respectively correspond to the active surfaces of the electronic devices, and the piezoelectric heat dissipation units are electrically connected to the conducting unit exposed by the first opening and the second opening.

### Claim 12 (depends on 11)

The manufacturing method of the package structure as recited in claim 11, wherein the step of providing the circuit substrate comprises:
providing a dielectric layer, wherein the dielectric layer has an upper surface and a lower surface opposite to each other and a plurality of holes;
disposing the electronic devices in the holes of the dielectric layer;
forming an insulating layer on the dielectric layer, wherein the insulating layer covers the upper surface and the lower surface of the dielectric layer and is filled in the holes to cover the electronic devices;
forming a plurality of through-holes extended from the first surface and the second surface of the core layer to the electronic devices, wherein the through-holes are electrically connected to the electronic devices;
forming a plurality of first pads on the first surface and the second surface of the core layer, wherein the first pads are electrically connected to the active surfaces of the electronic devices via a portion of the through-holes;
forming a plurality of second pads on the first surface and the second surface of the core layer, wherein the second pads surround the first pads; and
forming a plurality of third pads on the first surface and the second surface of the core layer, wherein the third pads are electrically connected to the back surfaces of the electronic devices via another portion of the through-holes, and the through-holes, the first pads, the second pads, and the third pads define the conducting unit.

### Claim 13 (depends on 12)

The manufacturing method of the package structure as recited in claim 12, further comprising:
attaching a plurality of release films on the first pads and the second pads before the first build-up circuit structure and the second build-up circuit structure are formed on the first surface and the second surface of the core layer; and
removing the release films after the first opening and the second opening of the first build-up circuit structure and the second build-up circuit structure are formed to expose the first pads and the second pads.

### Claim 14 (depends on 12)

The manufacturing method of the package structure as recited in claim 12, wherein the first build-up circuit structure comprises a first dielectric layer and a plurality of first conductive vias, the first conductive vias pass through the first dielectric layer and are extended and disposed on a top surface of the first dielectric layer, and the first conductive vias are at least electrically connected to the third pads.

### Claim 15 (depends on 12)

The manufacturing method of the package structure as recited in claim 12, wherein the second build-up circuit structure comprises a second dielectric layer and a plurality of second conductive vias, the second conductive vias pass through the second dielectric layer and are extended and disposed on a bottom surface of the second dielectric layer, and the second conductive vias are at least electrically connected to the third pads.

### Claim 16 (depends on 12)

The manufacturing method of the package structure as recited in claim 12, wherein each of the piezoelectric heat dissipation units comprises:
an elastic sheet;
a piezoelectric block disposed on the elastic sheet;
a first adhesive layer disposed on the piezoelectric block;
a buffer layer disposed on the first adhesive layer;
a second adhesive layer disposed on the buffer layer; and
two electrode wires embedded in the second adhesive layer, the buffer layer, and the first adhesive layer, wherein each of the electrode wires has a first end and a second end opposite to each other, the first end is embedded in a surface of the second adhesive layer relatively far from the buffer layer and in direct contact with one of the first pads, and the second end is in direct contact with the piezoelectric block.

### Claim 17 (depends on 12)

The manufacturing method of the package structure as recited in claim 12, wherein the step of providing the circuit substrate further comprises:
forming a plurality of conductive columns passing through the core layer and extended and disposed on the first surface and the second surface of the core layer.

### Claim 18 (depends on 11)

The manufacturing method of the package structure as recited in claim 11, further comprising, after the piezoelectric heat dissipation units are disposed on the conducting unit exposed by the first opening and the second opening:
forming a third build-up circuit structure on the first build-up circuit structure, wherein the third build-up circuit structure covers the first build-up circuit structure and has a plurality of first heat dissipation holes, and the first heat dissipation holes are disposed corresponding to the first opening; and
forming a fourth build-up circuit structure on the second build-up circuit structure, wherein the fourth build-up circuit structure covers the second build-up circuit structure and has a plurality of second heat dissipation holes, and the second heat dissipation holes are disposed corresponding to the second opening.

### Claim 19 (depends on 18)

The manufacturing method of the package structure as recited in claim 18, wherein the fourth build-up circuit structure comprises a build-up dielectric layer and a plurality of build-up conductive vias, the build-up dielectric layer covers the second build-up circuit structure, the build-up conductive vias pass through the build-up dielectric layer and are extended and disposed on an outer surface of the build-up dielectric layer, and the build-up conductive vias are at least electrically connected to the second conductive vias.

### Claim 20 (depends on 19)

The manufacturing method of the package structure as recited in claim 19, further comprising, after the fourth build-up circuit structure is formed:
forming a plurality of solder balls on the conductive vias extended and disposed on the outer surface of the build-up dielectric layer.