# US 9,883,129 B2 · Semiconductor device

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- Number: US 9,883,129 B2
- Document ID: US9883129B2
- Status: Granted
- Kind: B2
- Application number: 15/274,312
- Filed: 2016-09-23
- Published: 2017-03-30
- Granted: 2018-01-30
- Earliest claimed: 2015-09-25
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yoshiyuki Kurokawa
- Web page: https://patentgrep.com/patent/US9883129B2

## CPC

- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 9/8042: {involving data reduction}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H10F 39/80377: {characterised by the channel of the transistor, e.g. channel having a doping gradient}
- H10F 39/8063: {Microlenses}
- H10F 39/809: {of hybrid image sensors}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

The present invention provides a semiconductor device which enables data compression with a small amount of data. The present invention is a semiconductor device which includes a pixel portion, a memory, a first circuit, and a second circuit. The pixel portion has a function of obtaining imaging data. The first circuit has a function of performing discrete cosine transform on the imaging data, and generating first data. The first data is analog data, and the memory has a function of retaining the first data. The second circuit has a function of performing discrete cosine transform on the first data, and generating second data. The memory includes a first transistor, which includes an oxide semiconductor in a channel formation region, and a second transistor, in which a channel formation region is provided in a Si wafer.

## Claims

### Claim 1

A semiconductor device comprising:
a pixel portion configured to obtain an imaging data;
a first circuit configured to perform discrete cosine transform on the imaging data and generate a first data which is an analog data;
a memory configured to store the first data; and
a second circuit configured to perform discrete cosine transform on the first data and generate a second data.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the pixel portion comprises a photodiode and a transistor, and
wherein a channel formation region of the transistor comprises an oxide semiconductor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein each of the first circuit and the second circuit is an analog processing circuit.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the first circuit is configured to perform discrete cosine transform in one of the x-axis direction and the y-axis direction on the imaging data, and
wherein the second circuit is configured to perform discrete cosine transform in the other of the x-axis direction and the y-axis direction on the first data.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein the memory comprises a first transistor, a second transistor, and a capacitor,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

### Claim 6 (depends on 1)

A camera module comprising:
the semiconductor device according to claim 1; and
a lens.

### Claim 7

A semiconductor device comprising:
a pixel portion configured to obtain a first imaging data, a second imaging data, and a third imaging data which is a difference between the first imaging data and the second imaging data;
a first circuit configured to perform discrete cosine transform on the third imaging data and generate a first data which is an analog data;
a memory configured to store the first data; and
a second circuit configured to perform discrete cosine transform on the first data and generate a second data.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7,
wherein the pixel portion comprises a photodiode and a transistor, and
wherein a channel formation region of the transistor comprises an oxide semiconductor.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein each of the first circuit and the second circuit is an analog processing circuit.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7,
wherein the first circuit is configured to perform discrete cosine transform in one of the x-axis direction and the y-axis direction on the third imaging data, and
wherein the second circuit is configured to perform discrete cosine transform in the other of the x-axis direction and the y-axis direction on the first data.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7,
wherein the memory comprises a first transistor, a second transistor, and a capacitor,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

### Claim 12 (depends on 7)

A camera module comprising:
the semiconductor device according to claim 7; and
a lens.