# US 9,882,752 B2 · Method and apparatus for generating a multi-level pseudo-random test signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,752 B2 - Document ID: US9882752B2 - Status: Granted - Kind: B2 - Application number: 14/864,447 - Filed: 2015-09-24 - Published: 2016-03-24 - Granted: 2018-01-30 - Earliest claimed: 2014-09-24 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Marcel A. Kossel - Web page: https://patentgrep.com/patent/US9882752B2 ## CPC - H04L 25/4917: {using multilevel codes} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output. ## Claims ### Claim 1 A method for generating multi-level pseudo-random bit sequence (PRBS) patterns, the method comprising the steps of: providing a binary PRBS signal with a binary bit pattern sequence; and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output; wherein one symbol of a list of symbols is sequentially output each time state machines are triggered by a bit tester, the bit tester providing a first trigger signal for triggering a first state machine and a second trigger signal for triggering a second state machine for each of one or more clock cycles, wherein the state machines subsequently provide positive and negative symbols according to the binary PRBS signal, with each of the binary PRBS signals being different, and wherein the multilevel output is synchronized to a clock signal and transmitted via a transmission channel. ### Claim 2 (depends on 1) The method according to claim 1, wherein the symbol level is represented by a level of an electrical quantity, particularly of a voltage. ### Claim 3 (depends on 2) The method according to claim 2, wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols. ### Claim 4 (depends on 3) The method according to claim 3, wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign. ### Claim 5 (depends on 4) The method according to claim 4, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 6 (depends on 4) The method according to claim 4, wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols. ### Claim 7 (depends on 6) The method according to claim 6, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 8 (depends on 3) The method according to claim 3, wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols. ### Claim 9 (depends on 8) The method according to claim 8, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 10 (depends on 2) The method according to claim 2, wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols. ### Claim 11 (depends on 10) The method according to claim 10, wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign. ### Claim 12 (depends on 11) The method according to claim 11, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 13 (depends on 11) The method according to claim 11, wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols. ### Claim 14 (depends on 13) The method according to claim 13, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 15 (depends on 10) The method according to claim 10, wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols. ### Claim 16 (depends on 15) The method according to claim 15, wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order. ### Claim 17 An apparatus for generating multi-level pseudo-random bit sequence (PRBS) patterns for testing purposes, comprising: a PRBS generator for providing a binary PRBS signal with a binary bit pattern sequence; and a mapping unit for mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output; wherein one symbol of a list of symbols is sequentially output each time state machines are triggered by a bit tester, the bit tester providing a first trigger signal for triggering a first state machine and a second trigger signal for triggering a second state machine for each of one or more clock cycles, wherein the state machines subsequently provide positive and negative symbols according to the binary PRBS signal, with each of the binary PRBS signals being different, and wherein the multilevel output is synchronized to a clock signal and transmitted via a transmission channel. ### Claim 18 (depends on 17) The apparatus according to claim 17, the apparatus further comprising: a state machine for each state of the binary PRBS signal, wherein the state machine is triggered by the bit tester, depending on a state of the binary PRBS signal. ### Claim 19 (depends on 18) The apparatus according to claim 18, the apparatus further comprising: a signal combining unit for combining outputs of the state machines to obtain the multilevel output.