# US 9,882,708 B2 · Multi-rate transceiver circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,708 B2 - Document ID: US9882708B2 - Status: Granted - Kind: B2 - Application number: 15/047,413 - Filed: 2016-02-18 - Published: 2016-06-09 - Granted: 2018-01-30 - Earliest claimed: 2014-04-04 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Boon Hong Oh; Chee Wai Yap - Web page: https://patentgrep.com/patent/US9882708B2 ## CPC - H04L 7/0332: {with an integrator-detector} - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection} - G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline - H04N 7/015: High-definition television systems - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. ## Claims ### Claim 1 A method comprising: receiving a data stream at a receiver circuit; with a detector circuit in the receiver circuit, detecting data rate of the data stream received; with a controller block in the receiver circuit, configuring a deserializer circuit in the receiver circuit based on the data rate of the data stream; and irrespective of the data rate of the data stream received, receiving a constant reference clock signal at the receiver circuit. ### Claim 2 (depends on 1) The method defined in claim 1, wherein configuring the deserializer circuit comprises: setting a data width of the deserializer circuit based on the data rate of the data stream; and setting a frequency of a recovered clock signal based on the data rate of the data stream. ### Claim 3 (depends on 1) The method defined in claim 1, wherein the receiver circuit operates at a predetermined data rate, the method further comprising: with an oversampling circuit in the receiver circuit, oversampling the data stream by a factor that is calculated based on the data rate of the data stream and the predetermined data rate. ### Claim 4 (depends on 1) The method defined in claim 1, wherein the receiver circuit comprises a plurality of protocol blocks, the method further comprising: selectively disabling at least a portion of the plurality of the protocol blocks based on the data rate of the data stream. ### Claim 5 Circuitry comprising: a deserializer circuit that receives a data stream, wherein the data stream has a data rate; an oversampling circuit that receives the data steam from the deserializer circuit; a descrambler circuit that receives the data stream from the oversampling circuit and that is configured to apply descrambling algorithms to the data stream, wherein a data width of the descrambler circuit is adjusted based on the data rate of the data stream; and a plurality of protocol blocks that receives the data stream from the descrambler circuit. ### Claim 6 (depends on 5) The circuitry defined in claim 5, wherein the oversampling circuit is configured to oversample the data stream based on the data rate of the data stream. ### Claim 7 (depends on 5) The circuitry defined in claim 5, further comprising: clock and data recovery circuitry that generates a recovered clock signal; and a rate detector circuit that receives the recovered clock signal from the clock and data recovery circuitry. ### Claim 8 (depends on 7) The circuitry defined in claim 7, wherein the rate detector circuit is configured to determine the frequency of the recovered clock signal. ### Claim 9 (depends on 8) The circuitry defined in claim 8, wherein the rate detector circuit generates a video rate output signal based on the frequency of the recovered clock signal. ### Claim 10 (depends on 5) The circuitry defined in claim 5, further comprising: a video standard detector that receives the data stream from the deserializer circuit, wherein the video standard detector detects the data rate and the type of video standard of the data stream. ### Claim 11 (depends on 10) The circuitry defined in claim 10, further comprising: a reconfiguration controller coupled to the deserializer circuit; and a state machine that receives the data rate from the video standard detector and that initiates a reconfiguration of the deserializer via the reconfiguration controller based on the data rate. ### Claim 12 (depends on 11) The circuitry defined in claim 11, wherein the reconfiguration controller is configured to dynamically reconfigure the deserializer based on the data rate. ### Claim 13 (depends on 12) The circuitry defined in claim 12, wherein the reconfiguration controller is configured to dynamically reconfigure clock and data recovery circuitry within the deserializer based on the data rate. ### Claim 14 Circuitry comprising: a deserializer circuit that receives a data stream from an element that is external to the circuitry, wherein the deserializer circuit has an adjustable data width determined by a data rate associated with the data stream; and an oversampler circuit that receives the data stream from the deserializer circuit, wherein the oversampler circuit samples the data stream based on the data rate associated with the data stream and a predetermined data rate. ### Claim 15 (depends on 14) The circuitry defined in claim 14, wherein the deserializer circuit is configured to operate at an initial default data rate, and wherein the deserializer circuit is reconfigured during runtime based on the data rate associated with the data stream. ### Claim 16 (depends on 15) The circuitry defined in claim 15 further comprising: a control circuit that adjusts a data width of the deserializer circuit based on the data rate associated with the data stream. ### Claim 17 (depends on 15) The circuitry defined in claim 15, wherein the deserializer and the oversampler circuits form a receiver circuit, wherein the receiver circuit comprises: a plurality of protocol blocks coupled to the oversampler circuit, wherein the plurality of protocol blocks receives the data stream from the oversampler circuit, and wherein at least a portion of the plurality of protocol blocks is disabled based on the data rate associated with the data stream. ### Claim 18 (depends on 17) The circuitry defined in claim 17, wherein the plurality of protocol blocks comprises four protocol blocks, and wherein each protocol block of the four protocol blocks comprises a 20-bit input terminal and a 20-bit output terminal. ### Claim 19 (depends on 18) The circuitry defined in claim 18, wherein at least one of the four 20-bit input terminals and a respective 20-bit output terminal is disabled based on the data rate associated with the data stream.