# US 9,882,706 B1 · High speed transceiver

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- Number: US 9,882,706 B1
- Document ID: US9882706B1
- Status: Granted
- Kind: B1
- Application number: 15/392,244
- Filed: 2016-12-28
- Granted: 2018-01-30
- Earliest claimed: 2013-12-27
- Assignees: Inphi Corporation
- Applicants: Inphi Corporation
- Inventors: Marcel Louis Lugthart; Jeffrey Zachan; Linghsiao Jerry Wang; Paul Voois; Neel H. Patel; Norman L. Swenson; Scott Powell
- Web page: https://patentgrep.com/patent/US9882706B1

## CPC

- H04L 7/0062: {detection of error based on data decision error, e.g. Mueller type detection}
- H03M 5/12: Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
- H04B 1/40: Circuits
- H04L 5/14: Two-way operation using the same type of signal, i.e. duplex
- H04L 7/0016: {correction of synchronization errors}
- H04L 7/0037: {Delay of clock signal}
- H04L 7/0054: {Detection of the synchronisation error by features other than the received signal transition (by means of signal transition H04L7/033)}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission}
- H04L 25/03: Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver}
- H04L 27/02: Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation (H04L27/32 takes precedence)
- H04L 27/38: Demodulator circuits; Receiver circuits
- H04L 47/70: Admission control; Resource allocation
- H04L 7/02: Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)}
- H04L 25/03006: {Arrangements for removing intersymbol interference}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04B: TRANSMISSION

## Abstract

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

## Claims

### Claim 1

A transceiver comprising:
a host-side interface configured to receive a plurality of host-side transmit data signals from a host device and to transmit a plurality of host-side receive data signals to the host device;
a transmit path processor configured to multiplex the plurality of host-side transmit data signals to generate a line-side transmit data signal, wherein the line-side transmit data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side transmit data signals;
wherein the line-side transmit data signal is differential, wherein the transceiver further comprises a differential transmitter configured to output the line-side transmit data signal;
wherein the differential transmitter comprises a first digital-to-analog converter (DAC) configured to generate a first component of the line-side transmit data signal and a second DAC configured to generate a second component of the line-side transmit data signal;
a line-side interface configured to transmit the line-side transmit data signal over an electrical cable, wherein the line-side interface is further configured to receive a line-side receive data signal from the electrical cable;
a receive path processor configured to demultiplex the line-side receive data signal to generate the plurality of host-side receive data signals, wherein the line-side receive data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side receive data signals; and
a skew adjustment circuit configured to provide skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC.

### Claim 2 (depends on 1)

The transceiver of claim 1, wherein the plurality of host-side transmit data signals comprise a plurality of binary coded signals, and the line-side transmit data signal comprises a pulse amplitude modulation signal of at least four modulation levels.

### Claim 3 (depends on 1)

The transceiver of claim 1, wherein the line-side transmit data signal operates at a data rate of at least 40 Gbit/s.

### Claim 4 (depends on 1)

The transceiver of claim 1, further comprising a clock-and-data recovery circuit configured to generate a recovered clock signal and a recovered data signal from the line-side receive data signal, wherein the clock-and-data recovery circuit comprises a data recovery path and a clock recovery path separate from the data recovery path.

### Claim 5 (depends on 4)

The transceiver of claim 4, wherein the data recovery path comprises a data recovery analog-to-digital converter (ADC) configured to generate the recovered data signal, and wherein the clock recovery path comprises a clock recovery ADC configured to generate the recovered clock signal.

### Claim 6 (depends on 5)

The transceiver of claim 5, wherein the data recovery ADC has a higher resolution than the clock recovery ADC.

### Claim 7 (depends on 1)

The transceiver of claim 1, implemented on a single integrated circuit (IC).

### Claim 8

An active cable comprising:
an electrical cable comprising a first pair of conductors and a second pair of conductors; and
a pluggable transceiver module comprising:
a host-side interface configured to connect to a host device, the host-side interface configured to receive a plurality of host-side transmit data signals and to transmit a plurality of host-side receive data signals;
a transmit path processor configured to multiplex the plurality of host-side transmit data signals to generate a line-side transmit data signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side transmit data signals;
wherein the line-side transmit data signal is differential, wherein the pluggable transceiver module further comprises a differential transmitter configured to output the line-side transmit data signal;
a line-side interface configured to transmit the line-side transmit data signal over the first pair of conductors and to receive a line-side receive data signal from the second pair of conductors;
wherein the differential transmitter comprises a first digital-to-analog converter (DAC) configured to generate a first component of the line-side transmit data signal and a second digital-to-analog converter (DAC) configured to generate a second component of the line-side transmit data signal, the pluggable transceiver module further comprising a skew adjustment circuit configured to provide skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC; and
a receive path processor configured to demultiplex the line-side receive data signal to generate the plurality of host-side receive data signals, wherein the line-side receive data signal has a higher data rate and a higher level of encoding relative to each of the plurality of host-side receive data signals.

### Claim 9 (depends on 8)

The active cable of claim 8, wherein the pluggable transceiver module comprises a quad small form-factor pluggable (QSFP) port.

### Claim 10 (depends on 8)

The active cable of claim 8, wherein the first pair of conductors comprises a first pair of micro coaxial cables, and the second pair of conductors comprises a second pair of micro coaxial cables.

### Claim 11 (depends on 8)

The active cable of claim 8, wherein the line-side transmit data signal operates at a data rate of at least 40 Gbit/s.

### Claim 12 (depends on 8)

The active cable of claim 8, further comprising a clock-and-data recovery circuit configured to generate a recovered clock signal and a recovered data signal from the line-side receive data signal, wherein the clock-and-data recovery circuit comprises a data recovery path and a clock recovery path separate from the data recovery path.

### Claim 13 (depends on 12)

The active cable of claim 12, wherein the data recovery path comprises a data recovery analog-to-digital converter (ADC) configured to generate the recovered data signal, and wherein the clock recovery path comprises a clock recovery analog-to-digital converter (ADC) configured to generate the recovered clock signal, wherein the data recovery ADC has a higher resolution than the clock recovery ADC.

### Claim 14

A method of high speed communication in a transceiver, the method comprising:
receiving a plurality of host-side transmit data signals from a host device;
multiplexing the plurality of host-side transmit data signals to generate a line-side transmit data signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side transmit data signals;
wherein the line-side transmit data signal is differential, and wherein generating the line-side transmit data signal comprises generating, by a first digital-to-analog converter (DAC) of a differential transmitter, a first component of the line-side transmit data signal, and generating, by a second digital-to-analog converter (DAC) of the differential transmitter, a second component of the line-side transmit data signal;
transmitting the line-side transmit data signal over an electrical cable;
receiving a line-side receive signal from the electrical cable;
demultiplexing the line-side receive signal to generate a plurality of host-side receive data signals, the line-side receive signal of a higher data rate and of a higher level of encoding relative to each of the plurality of host-side receive data signals;
transmitting the plurality of host-side receive data signals to the host device and
providing, by a skew adjustment circuit, a skew adjustment to the differential transmitter based on adjusting a delay of a first clock signal of the first DAC relative to a second clock signal of the second DAC.