# US 9,882,577 B2 · Circuitry for use in comparators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,577 B2 - Document ID: US9882577B2 - Status: Granted - Kind: B2 - Application number: 15/455,957 - Filed: 2017-03-10 - Published: 2017-09-14 - Granted: 2018-01-30 - Earliest claimed: 2016-03-11 - Assignees: Socionext Inc. - Applicants: Socionext Inc. - Inventors: Ian Juso Dedic; Prabhu Ashwin Harold Rebello; John James Danson - Web page: https://patentgrep.com/patent/US9882577B2 ## CPC - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K 3/013: Modifications of generator to prevent operation by noise or interference - H03K 5/2481: {with at least one differential stage} - H03K 5/249: {using clock signals} - H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals. ## Claims ### Claim 1 Charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals, wherein: the circuitry comprises a controllable charge pump configured to provide said charge packet during said capture operation; the controllable charge pump is configured such that said charge packet has a given or predetermined size; and the controllable charge pump is configured to control said given or predetermined size, and the given or predetermined size is such that voltage levels at said first and second nodes settle at first and second different values during the capture operation in dependence upon the difference between magnitudes of the first and second input signals. ### Claim 2 (depends on 1) The charge-mode circuitry according to claim 1, wherein: the input signals are voltage-mode signals and the magnitudes are voltage levels; or the input signals are current-mode signals and the magnitudes are values of current; or the input signals are charge-mode signals and the magnitudes are amounts of charge; or the first and second input signals are analogue signals. ### Claim 3 (depends on 1) The charge-mode circuitry according to claim 1, wherein the control circuitry comprises switching circuitry provided along said paths, the switching circuitry configured such that the conductivity of the connections between the tail node and the first and second nodes is controlled by the magnitudes of the first and second input signals. ### Claim 4 (depends on 3) The charge-mode circuitry according to claim 3, wherein the switching circuitry comprises a first transistor whose channel forms part of the first path and a second transistor whose channel forms part of the second path, and wherein gate terminals of those transistors are controlled by the first and second input signals. ### Claim 5 (depends on 1) The charge-mode circuitry according to claim 1, wherein the control circuitry is configured to cause the charge packet to be divided so that portions thereof pass simultaneously along said first and second paths, the relative size of those portions being dependent on the difference between the magnitudes of the first and second input signals. ### Claim 6 (depends on 1) The charge-mode circuitry according to claim 1, wherein the controllable charge pump is connected such that said charge packet is delivered to the tail node during the capture operation. ### Claim 7 (depends on 1) The charge-mode circuitry according to claim 1, wherein said controllable charge pump comprises a capacitor and switching circuitry operable to charge said capacitor prior to said capture operation and to discharge said capacitor during said capture operation so as to provide said charge packet. ### Claim 8 (depends on 1) The charge-mode circuitry according to claim 1, connected to receive a clock signal and configured to perform said capture operation based upon said clock signal. ### Claim 9 (depends on 1) A comparator comprising the charge-mode circuitry according to claim 1. ### Claim 10 (depends on 9) The comparator according to claim 9, comprising differential-input dynamic or clocked latch circuitry, such as strongARM latch circuitry, the latch circuitry connected to receive its inputs from said charge-mode circuitry, optionally from said first and second nodes of the charge-mode circuitry. ### Claim 11 (depends on 1) Analogue-to-digital converter circuitry, comprising the charge-mode circuitry according to claim 1. ### Claim 12 (depends on 1) An IC chip, comprising the charge-mode circuitry according to claim 1. ### Claim 13 (depends on 9) Analogue-to-digital converter circuitry, comprising the comparator according to claim 9. ### Claim 14 (depends on 9) An IC Chip, comprising the comparator according to claim 9. ### Claim 15 (depends on 11) An IC Chip, comprising the analogue-to-digital converter circuitry according to claim 11.