# US 9,882,575 B1 · Analog-to-digital converter with offset calibration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,575 B1 - Document ID: US9882575B1 - Status: Granted - Kind: B1 - Application number: 15/293,740 - Filed: 2016-10-14 - Granted: 2018-01-30 - Earliest claimed: 2016-10-14 - Assignees: Analog Devices, Inc. - Applicants: Analog Devices, Inc. - Inventors: Hongxing Li; Michael C. W. Coln; Michael Mueck - Web page: https://patentgrep.com/patent/US9882575B1 ## CPC - H03M 1/1023: {Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295)} - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits - H03M 1/1245: {Details of sampling arrangements or methods} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An analog-to-digital converter (ADC) circuit including error correction circuitry for correcting offset drifts in an ADC, such as a successive approximation register (SAR) ADC. The offset drifts can be reduced, such as by sampling the offset following an analog-to-digital conversion and subsequently providing an error correction signal based on the sampled offset. ## Claims ### Claim 1 A method of providing error correction in an analog-to-digital conversion system, the method comprising: sampling a first analog signal using a sampling switch, and converting the sampled first analog signal into a first digital value; sampling a second analog signal that includes a digital-to-analog conversion of the first digital value wherein, the sampling including closing and re-opening of the sampling switch, converting the sampled second analog signal into a second digital value; and providing a digital error correction signal based on a difference between the first digital value and the second digital value. ### Claim 2 (depends on 1) The method of claim 1 further comprising converting the sampled first analog signal to the first digital value using a first analog to digital converter (ADC) and converting the sampled second analog signal to the second digital value using a second ADC. ### Claim 3 (depends on 1) The method of claim 1 further comprising converting the sampled first analog signal to the first digital value using an ADC, storing the first digital value in a register, and then converting the sampled second analog signal to the second digital value. ### Claim 4 (depends on 1) The method of claim 1 further comprising digitally filtering the digital error correction value. ### Claim 5 (depends on 4) The method of claim 4 further comprising: providing the digitally filtered error correction value to a digital-to-analog converter (DAC); converting the digitally filtered error correction value to an analog error correction signal; and adding the analog error correction signal to the sampled first analog signal. ### Claim 6 (depends on 1) The method of claim 1 wherein the first digital value includes a first additive error introduced by sampling the first analog signal, the second digital value includes a second additive error introduced by sampling the second analog signal, and the first additive error and the third additive error include contributions from a sampling pedestal effect. ### Claim 7 A method of providing error correction in an analog-to-digital conversion system, the system including a first capacitor digital-to-analog converter (CDAC), the method comprising: sampling a first analog signal onto the first CDAC using a sampling switch, and converting the sampled first analog signal into a first digital value; storing the first digital value in the first CDAC to produce a second analog signal; sampling the second analog signal converting the sampled second analog signal into a second digital value; and providing a corrected digital value based on the difference between the first digital value and the second digital value. ### Claim 8 (depends on 7) The method of claim 7 further comprising providing a digital error correction value to the input of the first CDAC to reduce an additive error introduced by sampling. ### Claim 9 (depends on 7) The method of claim 7 further comprising loading an upper portion of the first CDAC with a digital value based on the conversion of the first analog signal to a first digital value, then converting the second analog signal to a second digital value using a lower portion of the first CDAC. ### Claim 10 (depends on 9) The method of claim 9 further comprising providing a digital error correction value to the input of the lower portion of the first CDAC to reduce an additive error introduced by sampling. ### Claim 11 (depends on 7) The method of claim 7 further comprising coupling a second CDAC to the first CDAC and converting the second analog signal to a second digital value is performed using the second CDAC. ### Claim 12 (depends on 11) The method of claim 11 further comprising providing a digital error correction value to the input of the second CDAC to reduce an additive error introduced by sampling. ### Claim 13 (depends on 7) The method of claim 7 wherein the first digital value includes a first additive error introduced by sampling the first analog signal, the second digital value includes a second additive error introduced by sampling the second analog signal, and the first additive error and the second additive error include contributions from a pedestal effect. ### Claim 14 An analog-to-digital conversion system for converting an analog signal to a digital value and providing error correction, the system comprising: a first capacitor digital-to-analog converter (CDAC) configured to sample a first analog signal, the sampling introducing a first additive error to the sampled first analog signal; an analog-to-digital converter (ADC) configured to convert the sampled first analog signal to a first digital value, the converting introducing a second additive error to the first digital value; a second CDAC configured to sample a third additive error created by the closing and re-opening of a sampling switch, wherein the ADC converts the sampled third additive error to a second digital value, the converting introducing a fourth additive error to the second digital value; and a summation circuit configured to provide a corrected ADC digital value based on the difference between the first digital value and the second digital value. ### Claim 15 (depends on 14) The system of claim 14 wherein the second CDAC is further configured to receive an error correction value based on digitally filtered second digital values. ### Claim 16 (depends on 14) The system of claim 14 wherein the first additive error is approximately equal to the third additive error and the second additive error is approximately equal to the fourth additive error. ### Claim 17 (depends on 14) The system of claim 14 wherein the first CDAC includes capacitive elements corresponding to n digital bits and the second CDAC includes capacitive elements corresponding to m digital bits, and n is greater than m. ### Claim 18 An analog-to-digital conversion system for converting an analog signal to a digital value and providing error correction, the system comprising: a capacitor digital-to-analog converter (CDAC) configured to sample a first analog signal, the sampling introducing a first additive error to the sampled first analog signal; an analog-to-digital converter (ADC) configured to convert the sampled first analog signal to a first digital value, the converting introducing a second additive error to the first digital value; wherein a lower portion of the CDAC is then re-configured to sample a third additive error created by the closing and re-opening of a sampling switch, wherein the ADC converts the sampled third additive error to a second digital value, the converting introducing a fourth additive error to the second digital value; and a summation circuit configured to provide a corrected ADC digital value based on the difference between the first digital value and the second digital value. ### Claim 19 (depends on 18) The system of claim 18 wherein the lower portion of the CDAC is further configured to receive an error correction value based on digitally filtered second digital values. ### Claim 20 (depends on 18) The system of claim 18 wherein the first additive error is approximately equal to the third additive error and the second additive error is approximately equal to the fourth additive error.