# US 9,882,564 B1 · In line critical path delay measurement for accurate timing indication for a first fail mechanism

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,882,564 B1
- Document ID: US9882564B1
- Status: Granted
- Kind: B1
- Application number: 15/462,878
- Filed: 2017-03-19
- Granted: 2018-01-30
- Earliest claimed: 2017-03-19
- Assignees: PLSense Ltd.
- Applicants: Uzi Zangi; Neil Feldman
- Inventors: Uzi Zangi; Neil Feldman
- Web page: https://patentgrep.com/patent/US9882564B1

## CPC

- H03K 19/00323: {Delay compensation}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318328: {for delay tests}
- G01R 31/31858: {Delay testing}
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H03K 5/156: Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K 5/159: Applications of delay lines not covered by the preceding subgroups
- H03K 19/0008: {Arrangements for reducing power consumption}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.

## Claims

### Claim 1

An integrated circuit, compromising:
a first Flip Flop and a second Flip Flop;
a plurality of multiplexers;
a critical path delay built from plurality of combinational cells located between the first Flip Flop and a second Flip Flop, wherein a transition of an output signal of the first Flip Flop to a delay path cause a transition to an input of the second Flip Flop;
an in-line programmable Delay Line (DLL) connected to the output and input signals of the integrated circuit critical path, wherein an oscillation loop is created in two different options—with said DLL and without said DLL using different multiplexers of the plurality of multiplexers in the circuit;
a First Fail circuit built from a programmable Delay Line (DLL) having similar properties to the programmable Delay Line used inside the critical path configured to mimic an exact delay of the critical path in the integrated circuit;
wherein the First Fail circuit is in a configuration that gives a pass/fail indication;
a separate programmable voltage source connected to the First Fail circuit;
wherein the First Fail circuit is connected to a single voltage source different from the one used by the integrated circuit and receives an identical clock as the integrated circuit is using.

### Claim 2 (depends on 1)

The integrated circuit from claim 1, wherein the DLL is comprising from multiple stages and each stage is selected to either use a delay cell or to bypass this delay.

### Claim 3 (depends on 1)

The integrated circuit from claim 1, wherein the critical path is connected in a closed loop configuration wherein the output level is inverted from the input level create a toggling signal which frequency is measured by an external frequency tester.

### Claim 4 (depends on 1)

The integrated circuit from claim 1, wherein the critical path is connected through the DLL in a closed loop configuration wherein the output level is inverted from the input level to create a toggling signal which frequency is measured by an external frequency tester.

### Claim 5 (depends on 1)

The integrated circuit from claim 1, wherein a frequency which is measured using the oscillation loop configured to include the critical path plurality of cells and the said DLL, is configured, by changing the DLL code, to be half of the frequency of the oscillation loop that includes the critical path delay only, and therefore the DLL total delay is equal to the critical path delay using the selected code which represents the critical path delay.

### Claim 6 (depends on 1)

The integrated circuit from claim 1, wherein the First Fail circuit which includes an exact copy of the same programmable DLL as the one utilized as an in-line programmable Delay Line (DLL), is used to mimic the exact delay of the critical path using identical code which was obtained during the critical path delay measurement using the in-line DLL.

### Claim 7 (depends on 1)

The integrated circuit from claim 1, wherein a pass result at the First Fail circuit indicates that the given DLL delay is shorter than a used clock cycle and a fail result at the First Fail circuit indicates that the given DLL delay is longer than the used clock cycle.

### Claim 8 (depends on 1)

The integrated circuit from claim 1, wherein a minimum voltage at which the First Fail circuit outputs a pass result indicates a lowest possible voltage level to be used on the integrated circuit to optimize a integrated circuit power consumption.