# US 9,882,563 B2 · Method for reducing overdrive need in MOS switching and logic circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,882,563 B2
- Document ID: US9882563B2
- Status: Granted
- Kind: B2
- Application number: 13/853,305
- Filed: 2013-03-29
- Published: 2014-09-18
- Granted: 2018-01-30
- Earliest claimed: 2013-03-15
- Assignees: Dialog Semiconductor GmbH
- Applicants: Dialog Semiconductor B.V.
- Inventors: Michele Ancis; Rahul Todi
- Web page: https://patentgrep.com/patent/US9882563B2

## CPC

- H03K 19/0013: {in field effect transistor circuits}
- H03K 19/0021: {Modifications of threshold (for electronic switching or gating H03K17/30)}
- H03K 19/0027: {in field effect transistor circuits}
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

## Claims

### Claim 1

A method to lower signal range of a switching and/or logic circuit below supply range in order to optimize amplitude swing in regard of power consumption, the method comprising the steps of:
(1) providing a switching or logic circuit with positive and negative supply rails comprising one or more stages, wherein each stage comprises one or more transistors, a circuitry configured to driving the transistors, an input port, and an output port and wherein neighboring stages have input and output ports interconnected;
(2) lowering the signal range below the supply range by adding for each circuit stage one or two generic device networks, wherein each generic device network comprises a voltage source configured to establish a voltage drop between the circuit and an associated supply rail, wherein the signal swings between a positive reference voltage, provided by the voltage drop in regard of the positive supply rail, and a negative reference voltage, provided by the voltage drop in regard of the negative supply rail, and wherein each of the voltage drops is constant and is independent of current flowing through the generic device networks;
(3) decoupling the signal range from biasing voltages by providing a DC biasing network comprising biasing voltage sources providing biasing voltages applied to gates of the transistors as required and corresponding resistors providing impedances required, wherein negative terminals of all said biasing voltage sources are directly connected to ground and wherein said biasing voltage sources are set separately of the one or two generic device networks; and
(4) providing AC signal coupling of active devices of the circuit by a capacitive network;
wherein the switching or logic circuit is configured to enable different voltage swings of each subsequent stages while using a same supply voltage by implementing a varying generic device network scheme for each stage and wherein the AC coupling network and the DC biasing network allow signal swings lower than threshold voltages of active devices of the circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein each stage of the circuit comprises a generic device Pull-Down network (PD) and a generic device Pull-Up network (PU), wherein a Pull-Up network (PU) network is a combination of devices able to tie the output of a stage to the upper reference voltage and a Pull-Down network (PD) network is a combination of devices able to tie the output of a stage to the lower reference voltage.

### Claim 3 (depends on 1)

The method of claim 1, wherein the method is used to build a family of combinational and sequential logic circuits.

### Claim 4 (depends on 3)

The method of claim 3, wherein the family of logic circuits includes pass transistor logic circuits.

### Claim 5 (depends on 4)

The method of claim 4, wherein the pass transistor logic circuits include latches and memory elements.

### Claim 6 (depends on 3)

The method of claim 3, wherein the family of logic circuits comprises AND, OR, INV, NAND, NOR, XOR, and XNOR logic circuits.

### Claim 7 (depends on 1)

The method of claim 1, wherein specific signal ranges for each circuit stage can be achieved by decreasing or increasing the voltage drop of the one or two generic device networks associated to the stage where the signal range should be adapted.

### Claim 8 (depends on 1)

The method of claim 1, wherein amplifiers/attenuators, both digitally and analogically controlled, are realized based on progression/modulation in the supply range from stage to stage.

### Claim 9 (depends on 1)

The method of claim 1, wherein the circuit is a MOS circuit.

### Claim 10 (depends on 1)

The method of claim 1, wherein the circuit is built using any of semiconductor technologies wherein one port is used to control current flow through other ports.

### Claim 11 (depends on 1)

The method of claim 1, further comprising defining drive strength of the signals of the circuit by setting accordingly the biasing voltages.

### Claim 12

A switching or logic circuit comprising one or more stages configured to providing a signal range below supply range in order to optimize amplitude swing in regard of power consumption, wherein each stage comprises one or more transistors configured to perform the switching or logic functions of the circuit, a circuitry configured to driving the transistors transistors configured to perform the switching or logic functions of the circuit, an input port, and an output port and wherein neighboring stages have input and output ports interconnected, comprising:
positive and negative supply rails;
one or two generic device networks implemented for each stage of the circuit adapted each to providing a positive and/or a negative reference voltage for each stage of the circuit while the reference voltages allow a signal range of each stage of the circuit below the supply range of the circuit, thus configured to enable different voltage swings of each stage while using a same supply voltage by implementing a varying generic device network scheme for each stage, wherein the supply range is provided by said positive and negative supply rails and wherein the reference voltages are constant and independent of currents flowing through the one or two generic device networks of each stage, wherein each generic network comprises a voltage source configured to establish a voltage drop between the circuit and an associated supply rail;
a DC biasing network biasing active devices of the circuit comprising biasing voltage sources providing biasing voltages applied to the gates of the transistors configured to perform the switching or logic functions as required and resistors providing impedances for biasing as required, wherein negative terminals of all said biasing voltage sources are directly connected to ground and wherein said biasing voltage sources are set separately of the one or two generic device networks; and
an AC coupling network of capacitive means to couple AC signals of a stage to a neighboring stage;
wherein the AC coupling network and the DC biasing network allow signal swings lower than threshold voltages of active devices of the circuit.

### Claim 13 (depends on 12)

The circuit of claim 12 wherein each stage of the circuit comprises a generic device pull-down network (PD) and a generic device pull-up network (PU), wherein a Pull-Up network (PU) network is a combination of devices able to tie the output of a stage to the upper reference voltage and a Pull-Down network (PD) network is a combination of devices able to tie the output of a stage to the lower reference voltage.

### Claim 14 (depends on 12)

The circuit of claim 12 wherein the circuit is adapted to decoupling the signal range from the DC biasing voltages by the DC biasing network and the AC coupling network allowing a signal swing lower than a threshold voltage of active devices of the circuit.

### Claim 15 (depends on 12)

The circuit of claim 12 wherein the circuit is a part of a family of combinational and sequential logic circuits.

### Claim 16 (depends on 15)

The circuit of claim 15 wherein the family of logic circuits includes pass transistor logic circuits.

### Claim 17 (depends on 16)

The circuit of claim 16 wherein the pass transistor logic circuits include latches and memory elements.

### Claim 18 (depends on 15)

The circuit of claim 15 wherein the family of logic circuits comprises AND, OR, INV, NAND, NOR, XOR, and XNOR logic circuits.

### Claim 19 (depends on 12)

The circuit of claim 12 wherein specific signal ranges for each circuit stage can be achieved by decreasing or increasing the voltage drop of the one or two generic device networks associated to the stage where the signal range should be adapted.

### Claim 20 (depends on 12)

The circuit of claim 12 wherein drive strength of the signals of the circuit are defined by setting accordingly the biasing voltages.

### Claim 21 (depends on 12)

The circuit of claim 12 wherein the circuit is a MOS circuit.

### Claim 22 (depends on 12)

The circuit of claim 12 wherein the circuit is built using any of semiconductor technologies wherein one port is used to control current flow through other ports.