# US 9,882,555 B2 · Switch device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,555 B2 - Document ID: US9882555B2 - Status: Granted - Kind: B2 - Application number: 15/192,523 - Filed: 2016-06-24 - Published: 2017-12-28 - Granted: 2018-01-30 - Earliest claimed: 2016-06-24 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Andreas Meiser; Anton Mauder; Jens Barrenscheen - Web page: https://patentgrep.com/patent/US9882555B2 ## CPC - H03K 17/063: {in field-effect transistor switches} - H03K 17/18: Modifications for indicating state of switch - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/658: {having trench gate electrodes} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/112: {comprising multiple field plate segments} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H03K 2017/6878: {using multi-gate field-effect transistors} - H10D 62/152: {Source regions of DMOS transistors} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible. ## Claims ### Claim 1 A switch device, comprising: a switch transistor including a control terminal, a first load terminal and a second load terminal, and a monitoring component configured to monitor a signal at the control terminal of the switch transistor, wherein the monitoring component is configured to monitor an effect of a signal at the control terminal independent of a load current or voltage at the load terminals. ### Claim 2 (depends on 1) The switch device of claim 1, wherein the monitoring component and the switch transistor are provided on a same chip die. ### Claim 3 (depends on 1) The switch device of claim 1, wherein the monitoring component is configured to monitor the signal at a gate terminal essentially without influencing a load path including the first and second load terminals. ### Claim 4 (depends on 1) The switch device of claim 1, wherein the monitoring component is configured to monitor the signal at a gate terminal while no current flows between the first and second load terminals. ### Claim 5 (depends on 1) The switch device of claim 1, wherein the monitoring component comprises a further transistor, a control terminal of the further transistor being coupled to the control terminal of the switch transistor. ### Claim 6 (depends on 5) The switch device of claim 5, wherein the control terminal of the further transistor and the control terminal of the switch transistor are implemented in a common gate structure. ### Claim 7 (depends on 5) The switch device of claim 5, wherein the second load terminal of the switch transistor and a second load terminal of the further transistor are commonly coupled to one of a negative supply voltage or ground. ### Claim 8 (depends on 7) The switch device of claim 7, wherein the second load terminal of the switch transistor and the second load terminal of the further transistor are source terminals. ### Claim 9 (depends on 5) The switch device of claim 5, wherein a first load terminal of the further transistor is coupled to a feedback monitoring circuit configured to evaluate a signal received from the further transistor. ### Claim 10 (depends on 1) The switch device of claim 1, wherein the switch transistor comprises a further control terminal. ### Claim 11 (depends on 10) The switch device of claim 10, further comprising a further monitoring component associated with the further control terminal, the further monitoring component being configured to monitor a further signal applied to the further control terminal. ### Claim 12 (depends on 10) The switch device of claim 10, wherein the control terminal and the further control terminal are gate terminals. ### Claim 13 (depends on 1) The switch device of claim 1, wherein the first load terminal of the switch transistor is to be coupled to a first terminal of a load, the switch device further comprising a further switch transistor to be coupled to a second terminal of the load. ### Claim 14 (depends on 1) The switch device of claim 1, wherein the monitoring component comprises at least one of a feedback path from the control terminal of the switch transistor, a capacitive coupling to a load path including the first and second load terminals of the switch transistor or a feedback for a potential of the switch transistor connected to a load. ### Claim 15 A method, comprising: applying a test control signal to a switch device, the switch device comprising a switch transistor including a control terminal and first and second load terminals and a monitoring component, wherein the monitoring component is configured to monitor an effect of a signal at the control terminal independent of a load current or voltage at the load terminals, and evaluating the test control signal in the switch independent from a load path comprising the first and second load terminals. ### Claim 16 (depends on 15) The method of claim 15, wherein applying the test control signal comprises applying the test control signal while no load current is flowing via the first and second load terminals. ### Claim 17 (depends on 16) The method of claim 16, further comprising deactivating a further switch transistor, the further switch transistor being coupled to a first terminal of a load and the switch transistor being coupled to a second terminal of the load, while applying the test control signal. ### Claim 18 (depends on 16) The method of claim 16, wherein the switch transistor comprises a first control terminal and a second control terminal, wherein the method comprises applying the test control signal to the first control terminal while applying a further signal with an inactive signal level to the second control terminal. ### Claim 19 A switch device, comprising: a switch transistor, a monitoring transistor, wherein a control terminal of the monitoring transistor is coupled to a control terminal of the switch transistor, wherein a first load terminal of the switch transistor is to be coupled to a load, wherein a first load terminal of the monitoring transistor is coupled to a monitor circuit, wherein the first load terminal of the monitoring transistor is different than the first load terminal of the switch transistor, wherein a second load terminal of the switch transistor is coupled to a second load terminal of the monitoring transistor, and wherein the monitoring transistor is configured to monitor a signal at the control terminal of the switch transistor independent of a load current or voltage at the load terminals.