# US 9,882,553 B2 · Semiconductor device and circuit protecting method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,553 B2 - Document ID: US9882553B2 - Status: Granted - Kind: B2 - Application number: 15/259,976 - Filed: 2016-09-08 - Published: 2017-06-22 - Granted: 2018-01-30 - Earliest claimed: 2015-12-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Man-Ho Kwan; Fu-Wei Yao; Ru-Yi Su; King-Yuen Wong - Web page: https://patentgrep.com/patent/US9882553B2 ## CPC - H03K 5/08: by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level. ## Claims ### Claim 1 A semiconductor device, comprising: a first transistor, arranged to generate an output signal according to a control signal; and a clamping circuit including a second transistor and a resistive element, wherein the clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level, and wherein the resistive element is coupled between a gate terminal of the second transistor and a source terminal of the first transistor. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the control signal is a voltage drop between a gate terminal of the first transistor and a source terminal of the first transistor, and the clamping circuit is arranged to clamp the control signal to the predetermined signal level when the input signal is higher than the predetermined signal level. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the clamping circuit is arranged to clamp a gate current on a gate terminal of the first transistor to a predetermined current when the input signal is higher than the predetermined signal level. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the first threshold voltage and the second threshold voltage have different polarities. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first transistor is an enhancement-mode high-electron-mobility transistor (E-HEMT) and the second transistor is a depletion-mode high-electron-mobility transistor (D-HEMT). ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein when the input signal exceeds the predetermined signal level, a first voltage drop between a gate terminal of the first transistor and a source terminal of the first transistor is higher than the first threshold voltage, and a second voltage drop between a gate terminal of the second transistor and a source terminal of the second transistor is smaller than the second threshold voltage. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein a first connecting terminal of the second transistor is arranged to receive the input signal; a second connecting terminal of the second transistor is arranged to couple to a gate terminal of the first transistor to output the control signal; a first connecting terminal of the first transistor is arranged to output the output signal; and a second connecting terminal of the first transistor is arranged to couple to a gate terminal of the second transistor. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the resistive element is arranged to adjust the predetermined signal level. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the resistive element is arranged to reduce the predetermined signal level. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the first transistor and the clamping circuit are integrated onto a single chip. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the resistive element is an adjustable resistor. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the resistive element is a passive device. ### Claim 14 A semiconductor device, comprising: a first transistor, arranged to generate an output signal according to a control signal; and a second transistor, arranged to clamp the control signal to a predetermined signal level; wherein the predetermined signal level is based on a threshold voltage of the second transistor; and wherein a first connecting terminal of the second transistor is arranged to receive an input signal; a second connecting terminal of the second transistor is arranged to couple to a gate terminal of the first transistor to output the control signal; a first connecting terminal of the first transistor is arranged to output the output signal; and a second connecting terminal of the first transistor is arranged to couple to a gate terminal of the second transistor. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein when the second transistor clamps the control signal to the predetermined signal level, a voltage drop between the gate terminal of the second transistor and a source terminal of the second transistor is smaller than the threshold voltage. ### Claim 16 (depends on 14) The semiconductor device of claim 14, further comprising: a resistive element, arranged to adjust the predetermined signal level. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the resistive element is coupled between the gate terminal of the second transistor and a source terminal of the first transistor. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the resistive element is arranged to reduce the predetermined signal level. ### Claim 19 A circuit protecting method, comprising: providing a first transistor to generate an output signal according to a control signal; providing a second transistor to generate the control signal according to an input signal; providing a resistive element coupled between a gate terminal of the second transistor and a source terminal of the first transistor for adjusting the predetermined signal level; and using the second transistor to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level. ### Claim 20 (depends on 19) The circuit protecting method of claim 19, wherein using the second transistor to clamp the control signal to the predetermined signal level when the input signal exceeds the predetermined signal level comprises: controlling a voltage drop between the gate terminal of the second transistor and a source terminal of the second transistor to be smaller than the second threshold voltage when the input signal exceeds the predetermined signal level.