# US 9,882,346 B2 · Laser module with simplified alignment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,882,346 B2 - Document ID: US9882346B2 - Status: Granted - Kind: B2 - Application number: 15/104,599 - Filed: 2014-12-10 - Published: 2016-10-27 - Granted: 2018-01-30 - Earliest claimed: 2013-12-20 - Assignees: Koninklijke Philips N.V. - Applicants: Koninklijke Philips N.V. - Inventors: Stephan Gronenborn; Gero Heusler; Ralf Gordon Conrads; Holger Moench - Web page: https://patentgrep.com/patent/US9882346B2 ## CPC - H01S 5/02476: {Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements} - H01S 5/02253: using lenses - H01S 5/0238: using marks - H01S 5/02469: {Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC} - H01S 5/0202: {Cleaving} - H01S 5/423: {having a vertical cavity} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 46/301: {for alignment} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 72/00: Interconnections or connectors in packages - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The invention describes carrier structure (100, 200) for assembling a semiconductor lighting module, comprising at least two sub carriers (110, 210) and an alignment structure (120, 130, 230, 232) mechanically coupling the sub carriers (110, 210). The alignment structure (120, 130, 230, 232) is adapted such that the mechanical coupling to at least a part of the sub carriers (110, 210) disappears during thermal mating the carrier structure (100, 200) on a carrier (110, 250). The alignment structure (120, 130, 230, 232) is further adapted to compensate a coefficient of thermal expansion of a material of the carrier (110, 250) being higher than a coefficient of thermal expansion of a material of the carrier structure (100, 200). The invention further describes a semiconductor chip comprising such a carrier structure (100, 200) and a semiconductor lighting module comprising the carrier structure (100, 200) or the semiconductor chip. The invention finally describes a corresponding method of manufacturing a semiconductor lighting module. The invention enables assembling of semiconductor lighting modules by thermal mating with reduced alignment effort. ## Claims ### Claim 1 A carrier structure for assembling a semiconductor lighting module comprising: at least two sub carriers and an alignment structure, the alignment structure mechanically coupling the sub carriers, wherein the alignment structure is arranged such that the mechanical coupling to at least a part of the sub carriers disappears during thermal mating of the carrier structure to a carrier, wherein the alignment structure is arranged to compensate for a coefficient of thermal expansion of a material of the carrier, wherein the thermal expansion of the material of the carrier is higher than a coefficient of thermal expansion of a material of the carrier structure, wherein the sub carriers are submounts for mounting semiconductor light sources, wherein the alignment structure comprises at least one first frame structure, wherein the at least one frame structure comprises at least one first bridge, for each submount, wherein the alignment structure mechanically couples the submounts to the first frame structure such that the submounts are arranged in parallel to the first frame structure, wherein the at least one first bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least one first bridge exceeds a threshold value, wherein at least one second frame structure comprises at least one second bridge for each submount, wherein the alignment structure mechanically couples the submounts to the second frame structure such that the submounts are arranged in parallel to the second frame structure, wherein the at least second bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least second bridge exceeds a threshold value. ### Claim 2 (depends on 1) A semiconductor chip comprising the carrier structure according to claim 1, the semiconductor chip comprising semiconductor light sources disposed on the sub carriers, wherein the carrier structure comprises at least parts of a substrate of the semiconductor chip and the alignment structure comprises a breaking line between at least a first sub carrier and a second sub carrier. ### Claim 3 (depends on 2) The semiconductor chip according to claim 2, wherein the alignment structure comprises holes in the substrate. ### Claim 4 (depends on 2) The semiconductor chip according to claim 2, wherein the alignment structure comprises trenches in the substrate. ### Claim 5 (depends on 4) The semiconductor chip according to claim 4, wherein a first trench is provided at the light emitting side of the semiconductor chip, wherein a second trench is provided at the side opposite to the light emitting side of the semiconductor chip in parallel to the first trench, wherein the depth of the first and the second trench is arranged such that both trenches overlap within the substrate. ### Claim 6 A method of manufacturing a semiconductor lighting module, the method comprising the steps of: providing a carrier structure comprising at least two sub carriers, wherein an alignment structure is mechanically coupled to the sub carriers, wherein the alignment structure is arranged such that the mechanical coupling to at least a part of the sub carriers disappears during thermal mating the carrier structure on a carrier, wherein the alignment structure is arranged to compensate for a coefficient of thermal expansion of a material of the carrier being higher than a coefficient of thermal expansion of a material of the carrier structure, wherein the sub carriers are submounts for mounting semiconductor light sources, wherein the alignment structure comprises at least one first frame structure, wherein the at least one frame structure comprises at least one first bridge, for each submount, wherein the alignment structure mechanically couples the submounts to the first frame structure such that the submounts are arranged in parallel to the first frame structure, wherein the at least one first bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least one first bridge exceeds a threshold value, wherein at least one second frame structure comprises at least one second bridge for each submount, wherein the alignment structure mechanically couples the submounts to the second frame structure such that the submounts are arranged in parallel to the second frame structure, wherein the at least second bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least second bridge exceeds a threshold value, providing at least two semiconductor light sources on the sub carriers; and thermal mating the carrier structure to the carrier. ### Claim 7 A semiconductor chip comprising: a carrier structure, the carrier structure comprising at least two sub carriers and an alignment structure, the alignment structure mechanically coupling the sub carriers; and semiconductor light sources disposed on the sub carriers, wherein the carrier structure comprises at least parts of a substrate of the semiconductor chip and the alignment structure comprises a breaking line between at least a first sub carrier and a second sub carrier, wherein the alignment structure is arranged such that the mechanical coupling to at least a part of the sub carriers disappears during thermal mating of the carrier structure to a carrier, wherein the alignment structure is arranged to compensate for a coefficient of thermal expansion of a material of the carrier, wherein the thermal expansion of the material of the carrier is higher than a coefficient of thermal expansion of a material of the carrier structure, wherein the alignment structure comprises holes in the substrate, wherein the holes are provided along at least two parallel lines and the holes of the first line are arranged staggered with respect to the holes of the second line, wherein an extension of the holes in parallel to the lines is bigger than a joint between two holes in the lines such that the joints of the first line can slide in a corresponding hole of the second line and joints of the second line can slide in a corresponding hole of the first line during thermal mating the carrier structure to the carrier. ### Claim 8 (depends on 7) The semiconductor chip according to claim 7, wherein the alignment structure comprises trenches in the substrate. ### Claim 9 (depends on 8) The semiconductor chip according to claim 8, wherein a first trench is provided at the light emitting side of the semiconductor chip, wherein a second trench is provided at the side opposite to the light emitting side of the semiconductor chip in parallel to the first trench, wherein the depth of the first trench and the second trench is arranged such that both trenches overlap within the substrate. ### Claim 10 (depends on 7) The semiconductor chip according to claim 7, wherein the semiconductor light sources comprise at least two laser arrays provided on the different sub carriers. ### Claim 11 (depends on 7) The semiconductor lighting module comprising at least two sub carriers of the carrier structure according to claim 7 thermally mated to a heat sink and at least two semiconductor light sources provided on different sub carriers. ### Claim 12 (depends on 11) The semiconductor lighting module according to claim 11, comprising an optical device disposed on top of the light emitting side of the semiconductor light sources. ### Claim 13 (depends on 12) The semiconductor lighting module according to claim 12, wherein the optical device is a microlens array. ### Claim 14 A carrier structure for assembling a semiconductor lighting module comprising: at least two sub carriers and an alignment structure, the alignment structure mechanically coupling the sub carriers; and at least one first alignment frame, the first alignment frame having at least one third alignment hole and at least one third bridge, wherein the at least one third bridge mechanically couples the at least one submount or the at least one frame structure to the first alignment frame, wherein the alignment structure is arranged such that the mechanical coupling to at least a part of the sub carriers disappears during thermal mating of the carrier structure to a carrier, wherein the alignment structure is arranged to compensate for a coefficient of thermal expansion of a material of the carrier, wherein the thermal expansion of the material of the carrier is higher than a coefficient of thermal expansion of a material of the carrier structure, wherein the sub carriers are submounts for mounting semiconductor light sources, wherein the alignment structure comprises at least one first frame structure, wherein the at least one frame structure comprises at least one first bridge, for each submount, wherein the alignment structure mechanically couples the submounts to the first frame structure such that the submounts are arranged in parallel to the first frame structure, wherein the at least one first bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least one first bridge exceeds a threshold value. ### Claim 15 (depends on 14) A semiconductor chip comprising the carrier structure according to claim 14, the semiconductor chip comprising semiconductor light sources disposed on the sub carriers, wherein the carrier structure comprises at least parts of a substrate of the semiconductor chip and the alignment structure comprises a breaking line between at least a first sub carrier and a second sub carrier. ### Claim 16 (depends on 15) The semiconductor chip according to claim 15, wherein the alignment structure comprises holes in the substrate. ### Claim 17 (depends on 15) The semiconductor chip according to claim 15, wherein the alignment structure comprises trenches in the substrate. ### Claim 18 (depends on 17) The semiconductor chip according to claim 17, wherein a first trench is provided at the light emitting side of the semiconductor chip, wherein a second trench is provided at the side opposite to the light emitting side of the semiconductor chip in parallel to the first trench, wherein the depth of the first and the second trench is arranged such that both trenches overlap within the substrate. ### Claim 19 A carrier structure for assembling a semiconductor lighting module comprising: at least two sub carriers and an alignment structure, the alignment structure mechanically coupling the sub carriers; at least one first alignment frame, the first alignment frame having at least one third alignment hole and at least one third bridge, wherein the at least one third bridge mechanically couples the at least one submount or the at least one frame structure to the first alignment frame; and a second alignment frame, the second alignment frame having at least one fourth alignment hole, wherein the at least one fourth bridge mechanically couples the at least one submount or the at least one frame structure to the second alignment frame, wherein the alignment structure is arranged such that the mechanical coupling to at least a part of the sub carriers disappears during thermal mating of the carrier structure to a carrier, wherein the alignment structure is arranged to compensate for a coefficient of thermal expansion of a material of the carrier, wherein the thermal expansion of the material of the carrier is higher than a coefficient of thermal expansion of a material of the carrier structure, wherein the sub carriers are submounts for mounting semiconductor light sources, wherein the alignment structure comprises at least one first frame structure, wherein the at least one frame structure comprises at least one first bridge, for each submount, wherein the alignment structure mechanically couples the submounts to the first frame structure such that the submounts are arranged in parallel to the first frame structure, wherein the at least one first bridge is arranged to break during thermal mating the carrier structure to the carrier if thermal stress exerted on the at least one first bridge exceeds a threshold value. ### Claim 20 (depends on 19) A semiconductor chip comprising the carrier structure according to claim 19, the semiconductor chip comprising semiconductor light sources disposed on the sub carriers, wherein the carrier structure comprises at least parts of a substrate of the semiconductor chip and the alignment structure comprises a breaking line between at least a first sub carrier and a second sub carrier. ### Claim 21 (depends on 20) The semiconductor chip according to claim 20, wherein the alignment structure comprises holes in the substrate. ### Claim 22 (depends on 20) The semiconductor chip according to claim 20, wherein the alignment structure comprises trenches in the substrate. ### Claim 23 (depends on 22) The semiconductor chip according to claim 22, wherein a first trench is provided at the light emitting side of the semiconductor chip, wherein a second trench is provided at the side opposite to the light emitting side of the semiconductor chip in parallel to the first trench, wherein the depth of the first and the second trench is arranged such that both trenches overlap within the substrate.