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US 9,876,501 B2Granted
Switching power amplifier and method for controlling the switching power amplifier
AssigneeMediatek Inc.
InventorsYang-Chuan Chen, Hsiang-Hui Chang
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Abstract
A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.
Claims28
A switching power amplifier, comprising:
- a first transistor, controlled by a first digital signal to selectively output a first output signal;
- a second transistor, controlled by a second digital signal to selectively output a second output signal;
- and
- a control circuit, arranged to generate the second digital signal according to the first digital signal and a third digital signal, the control circuit comprising an inverter that inverts the first digital signal, wherein a state of the first transistor is independent of the third digital signal;
- wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor, and the first digital signal and the third digital signal are a differential pair.
2 more elements
A method for controlling a switching power amplifier, wherein the switching power amplifier comprises a first transistor and a second transistor, and the method comprises:
- controlling the first transistor to selectively output a first output signal by a first digital signal;
- controlling the second transistor to selectively output a second output signal by a second digital signal;
- and
- generating the second digital signal according to an inverted version of the first digital signal and a third digital signal, wherein a state of the first transistor is independent of the third digital signal;
- wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor, and the first digital signal and the third digital signal are a differential pair.
2 more elements
A digital power amplifying device, comprising:
- a first switching power amplifier, comprising:
- a first transistor, controlled by a first digital signal to selectively output a first output signal;
- a second transistor, controlled by a second digital signal to selectively output a second output signal;
- and
- a first control circuit, arranged to generate the second digital signal according to the first digital signal and a third digital signal;
- wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor;
- a second switching power amplifier, comprising:
- a third transistor, controlled by a fourth digital signal to selectively output a third output signal;
- a fourth transistor, controlled by a fifth digital signal to selectively output a fourth output signal;
- and
- a second control circuit, arranged to generate the fifth digital signal according to the fourth digital signal and a sixth digital signal,
- wherein the third output signal and the fourth output signal are outputted on a common connected node of the first transistor and the second transistor, and
- wherein the first digital signal and the fourth digital signal are a differential pair.
10 more elements
A switching power amplifier, comprising:
- a first transistor, controlled by a first digital signal to selectively output a first output signal;
- a second transistor, controlled by a second digital signal to selectively output a second output signal;
- and
- a control circuit, arranged to generate the second digital signal according to the first digital signal and a third digital signal, wherein a state of the first transistor is independent of the third digital signal, and the first digital signal and the third digital signal are a differential pair,
- wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor,
- wherein the switching power amplifier further comprises a delay circuit, arranged to generate a delayed first digital signal according to the first digital signal,
- wherein the first transistor is controlled by the delayed first digital signal to selectively output the first output signal, and
- wherein the delay circuit comprises:
- an inverter, arranged to generate an inverted first digital signal according to the first digital signal;
- and
- a NAND gate, arranged to generate the delayed first digital signal according to the inverted first digital signal and a high voltage level.
8 more elements
A method for controlling a switching power amplifier, wherein the switching power amplifier comprises a first transistor and a second transistor, and the method comprises:
- controlling the first transistor to selectively output a first output signal by a first digital signal;
- controlling the second transistor to selectively output a second output signal by a second digital signal;
- and
- generating the second digital signal according to the first digital signal and a third digital signal, wherein a state of the first transistor is independent of the third digital signal, and the first digital signal and the third digital signal are a differential pair,
- wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor,
- wherein the method further comprises:
- generating a delayed first digital signal according to the first digital signal, wherein the first transistor is controlled by the delayed first digital signal to selectively output the first output signal,
- wherein the step of generating the delayed first digital signal according to the first digital signal comprises:
- using an inverter to generate an inverted first digital signal according to the first digital signal;
- and
- using a NAND gate to generate the delayed first digital signal according to the inverted first digital signal and a high voltage level.
8 more elements
Dependencies are inferred from the claim text.