Method of implementing a differential integrating phase interpolator

A phase interpolator comprising:

• a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source;
• a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source;
• and
• a transient bias loop control circuit for controlling current in a pair of first and second current sources and a common mode loop control circuit for controlling current in a pair of third and fourth current sources, where the pair of first and second current sources is one of a pair of the first and second pull-up current sources and a pair of the first and second pull-down current sources, and where the pair of the third and fourth current sources is the other of the pair of the first and second pull-up current sources and the pair of the first and second pull-down current sources.