System and method for a tunable capacitance circuit

A method for providing a tunable capacitance, the method comprising:

• providing a first capacitance using a plurality of switchable capacitance branches coupled in parallel, wherein each switchable capacitance branch comprises:
• a plurality of varactor transistor pairs which are coupled in series with each other via a coupling between first respective series terminals of respective varactor transistor pairs and second respective series terminals of adjacent respective varactor transistor pairs, wherein the coupling is coupled to a reference node, and wherein each varactor transistor pair of the plurality of varactor transistor pairs comprises:
• a first varactor transistor coupled in series to a second varactor transistor, wherein a source terminal and a drain terminal of the first varactor transistor are coupled to each other and to the first series terminal of the varactor transistor pair, wherein a source terminal and a drain terminal of the second varactor transistor are coupled to each other and to the second series terminal of the varactor transistor pair, and wherein a gate terminal of the first varactor transistor is coupled to a gate terminal of the second varactor transistor, wherein the varactor transistor pairs of each switchable capacitance branch are operated at a first respective bias condition;
• and
• providing a second capacitance using the plurality of switchable capacitance branches, wherein the varactor transistor pairs of each switchable capacitance branch are operated at a second respective bias condition.

A tunable capacitance circuit comprising:

• a plurality of varactor transistor pair elements coupled in series, wherein each varactor transistor pair element in the plurality of varactor transistor pair elements comprises:
• a first varactor transistor comprising a first gate terminal coupled to a tuning terminal of the varactor transistor pair element and comprising a first drain terminal coupled to a first source terminal and a first series terminal of the varactor transistor pair element, and
• a second varactor transistor coupled in series to the first varactor transistor and comprising a second gate terminal coupled to the first gate terminal of the first varactor transistor and coupled to the tuning terminal of the varactor transistor pair element and comprising a second drain terminal coupled to a second source terminal and a second series terminal of the varactor transistor pair element;
• wherein the second series terminal of a first varactor transistor pair element of the plurality of varactor transistor pair elements is connected to the first series terminal of a second varactor transistor pair element of the plurality of varactor transistor pair elements, the second series terminal of the first varactor transistor pair element and the first series terminal of the second varactor transistor pair element are coupled to a reference potential via an impedance element, and at least one bias resistor is respectively coupled between a tuning node and each respective tuning terminal of each of the plurality of varactor transistor pair elements.

A tunable capacitance circuit, comprising:

• a plurality of varactor transistor pairs coupled in series, wherein
• the varactor transistors of each of the plurality of varactor transistor pairs are coupled in series within the varactor transistor pair and are formed in or on a substrate, and wherein the substrate is biased such that drain-bulk diodes and source-bulk diodes of the varactor transistors are reverse-biased,
• a source terminal of a first field-effect transistor of a first varactor transistor pair of the plurality of varactor transistor pairs is coupled with a drain terminal of the first field-effect transistor,
• a source terminal of a second field-effect transistor of the first varactor transistor pair of the plurality of varactor transistor pairs is coupled with a drain terminal of the second field-effect transistor, and
• a gate terminal of the first field-effect transistor is coupled with a gate terminal of the second field-effect transistor, such that the first field-effect transistor acts as a first varactor transistor, and such that the second field-effect transistor acts as a second varactor transistor,
• a capacitance of the first field-effect transistor depends on a gate-source bias voltage applied to the first field-effect transistor, and
• a capacitance of the second field-effect transistor depends on a gate-source bias voltage applied to the second field-effect transistor;
• wherein the source terminal and the drain terminal of the second field-effect transistor are coupled to a reference potential via an impedance element, wherein the source terminal and the drain terminal of a third field effect transistor of a second varactor transistor pair of the plurality of varactor transistor pairs are coupled to the reference potential via the impedance element,
• the gate terminal of the first field-effect transistor and the gate terminal of the second field-effect transistor are coupled to a control voltage provider via a gate impedance element, and
• the control voltage provider is configured to switch a control voltage, which is applied to the gate terminals of the field-effect transistors, between two discrete values.