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US 9,876,114 B2Granted
Structure and method for 3D FinFET metal gate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShiu-Ko JangJian, Chih-Nan Wu, Chun Che Lin, Ting-Chun Wang
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Abstract
The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.
Claims20
A semiconductor structure, comprising:
- a semiconductor substrate;
- and
- a gate stack disposed on the semiconductor substrate;
- wherein the gate stack includes a high k dielectric material layer, and a plurality of metal layers disposed over the high-k dielectric material layer, wherein the gate stack has a convex top surface that includes a topmost surface of each of the plurality of metal layers.
1 more element
A semiconductor structure, comprising:
- a semiconductor substrate;
- and
- a gate stack disposed over the semiconductor substrate;
- wherein the gate stack includes
- a gate dielectric layer including a high k dielectric material;
- a capping layer disposed over the high k dielectric material layer;
- a work function metal layer disposed over the capping layer;
- a blocking layer disposed over the work function metal layer;
- and
- a filling metal layer disposed over the blocking layer,
- wherein the gate stack has a convex top surface including a topmost surface of the filling metal layer and a topmost surface of a gate stack layer from a group consisting of the gate dielectric layer, the capping layer, the work function layer, and the blocking layer.
8 more elements
A method of forming a semiconductor structure, comprising:
- forming a dummy gate over a semiconductor substrate;
- forming an interlayer dielectric layer over the substrate;
- removing the dummy gate, resulting in a gate trench in the interlayer dielectric layer;
- forming a plurality of gate material layers to fill in the gate trench, wherein the gate material layers include a gate dielectric layer and a plurality of metal layers, and further include a top surface that includes a first material of a first layer of the plurality of gate material layers and a second material of a second layer of the plurality of gate material layers;
- and
- performing a selective removing process on the top surface wherein the first material of the first layer and the second material of the second layer are removed at different rates, thereby forming a gate stack having a convex top surface that includes a first top surface of the first layer and a second top surface of the second layer.
3 more elements
Dependencies are inferred from the claim text.