Wiring substrate and semiconductor device

A semiconductor device comprising:

• a wiring substrate;
• and
• a semiconductor chip mounted on the wiring substrate;
• wherein the wiring substrate includes
• a first wiring structure, and
• a second wiring structure stacked on the first wiring structure;
• wherein the first wiring structure includes
• a first wiring layer,
• a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer, and
• a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring;
• the second wiring structure includes
• a second wiring layer including a first wiring pattern and a second wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insulating layer and the upper end surface of the via wiring, and wherein the second wiring pattern is formed on the upper surface of the first insulating layer,
• a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer, and
• an uppermost wiring layer on which the semiconductor chip is flip-chip mounted;
• the second wiring structure has a higher wiring density than the first wiring structure;
• the first wiring pattern comprises:
• a first metal barrier film formed on the upper surface of the first insulating layer and the upper end surface of the via wiring;
• a first metal film formed on the first metal barrier film;
• and
• a first metal layer formed on the first metal film, the first metal layer partially including a roughened surface, and partially including a smooth surface,
• wherein the roughened surface of the first metal layer has a smaller surface roughness than a surface roughness of the first wiring layer;
• and
• the second wiring pattern comprises:
• a second metal barrier film formed on the upper surface of the first insulating layer;
• a second metal film formed on the second metal barrier film;
• and
• a second metal layer formed on the second metal film,
• wherein the second metal barrier film includes a side surface located at an inner side of a side surface of the second metal layer.