Method for making 32-bit addressing of SV data by utilizing FPGA

A method for making 32-bit addressing of Sampling Value (SV) data by using a Field Programmable Gate Array (FPGA), in which the FPGA converts the received SV data conforming to IEC61850-9-2 protocol into data that may be read directly by 32-bit addressing processor, wherein the method comprises the following steps:

• (1) using the FPGA to receive Ethernet data;
• (2) the FPGA screening the received data through Ethernet message type code;
• a data with message type code of 0x88BA refers to SV data, which is further processed through the following steps;
• (3) memory units aligned in 32 bits being allocated for saving contents of Ethernet frame header in the SV data, data being copied during which data less than 32 bits is extended by filling 0, which is then saved in a memory;
• In the saved data, media access control data occupies three 32-bit units, while other data occupies one 32-bit unit;
• The contents of the Ethernet frame header include the following data:
• media access control data (MAC), priority and tags (Priority & tagged), datagram type code (Ethertype), application identity (APPID), length (Length), and reserved word (Reserved);
• (4) application protocol data unit (APDU) in the SV data being reorganized by using 32-bit alignment, which is achieved by:
• according to the IEC61850-9-2 protocol, the application protocol data unit in the SV data consists of a number of data units created based on Abstract Syntax Notation One (ASN.1) coding rules;
• the tag and length information of each data unit created based on the ASN.1 coding rules are used to create a 32-bit data and one memory unit aligned in 32 bits is allocated to save it, wherein data for each of the tag information and length information is 32 bits;
• data value is stored starting from next 32-bit memory unit;
• if any data unit created based on the ASN.1 coding rules is embedded in the data value, the foresaid procedure is repeated;
• (5) The SV data reorganized through the steps (3) and (4) being transmitted to and read by data processer DSP, wherein all the reorganized SV data are 32-bit aligned and stored.