Differential power analysis countermeasures
AssigneeCisco Technology, Inc.
InventorYaacov Belenky
Life of this patent
Estimating the term…
Abstract
An electronic device includes a plurality of logic units, which have respective inputs and outputs and are arranged in a ring topology, such that an input of each of the logic units is coupled to an output of another of the logic units. Each of the logic units includes respective processing logic, which is identical to and operates in synchrony with the processing logic of the other logic units to process respective data values using at least one secret value stored in the device. The logic units are coupled, at an initial cycle of the device, to receive respective input values that are mutually uncorrelated. At subsequent cycles of the device, each of the logic units receives and operates on intermediate values that are output by another of the logic units.
Claims20
An electronic device, comprising:
- a device input, coupled to receive a first input value;
- a device output;
- and
- a logic core, coupled to the device input so as to receive and process the first input value using a secret value stored in the logical core so as to provide an output value at the device output, the logic core comprising:
- an input generator, configured to provide a second input value that is uncorrelated with the first input value;
- and
- a plurality of logic units implemented in hardware, consisting essentially of:
- a first logic unit, comprising a first logic input, which is coupled to receive, at an initial cycle of the device, the first input value from the device input and to receive, at subsequent cycles of the device, first intermediate values generated by another one of the logic units;
- and first processing logic configured to operate on first data values provided by the first logic input using the secret value, thereby generating second intermediate values;
- and
- a second logic unit, comprising a second logic input, which is coupled to receive the second input value from the input generator at the initial cycle of the device and to receive, at subsequent cycles of the device, the second intermediate values;
- and second processing logic identical to the first processing logic and configured to operate, in synchrony with the first processing logic, on second data values provided by the second logic input, thereby generating further intermediate values for input to a further one of the logic units.
A method, comprising:
- receiving, at a device input of a device comprising a plurality of logic units implemented in hardware, a first input value;
- providing, in the device, a second input value that is uncorrelated with the first input value;
- and
- processing the first and second input values in a logic core consisting essentially of a plurality of logic units, using a secret value stored in the device, so as to provide an output value at a device output of the device,
- wherein the plurality of the logic units consist essentially of:
- a first logic unit, comprising a first logic input, which receives, at an initial cycle of the device, the first input value from the device input and receives, at subsequent cycles of the device, first intermediate values generated by another one of the logic units;
- and first processing logic operating on first data values provided by the first logic input using the secret value to generate second intermediate value;
- and
- a second logic unit, comprising a second logic input, which receives the second input value at the initial cycle of the device and receives, at subsequent cycles of the device, the second intermediate values;
- and second processing logic identical to the first processing logic and operating in synchrony with the first processing logic on second data values provided by the second logic input to generate further intermediate values for input to a further one of the logic units.
An electronic device, consisting essentially of a plurality of logic units implemented in hardware, which have respective inputs and outputs and are arranged in a ring topology, such that an input of each of the logic units is coupled to an output of another of the logic units,
- wherein each of the logic units comprises respective processing logic, which is identical to and operates in synchrony with the processing logic of the other logic units to process respective data values using at least one secret value stored in the device,
- wherein the logic units are coupled, at an initial cycle of the device, to receive respective input values that are mutually uncorrelated, and
- wherein at subsequent cycles of the device, each of the logic units receives and operates on intermediate values that are output by another of the logic units.
Dependencies are inferred from the claim text.