Digital to-analog converters with non-binary weighted cell array

A digital-to-analog converter (DAC) circuit configured to receive a digital signal comprising a plurality of bits and provide an analog signal, the circuit comprising:

• a first cell array comprising a first plurality of cells each being configured to receive a state of one bit from a first subset of the plurality of bits and provide an output based on the received state of the one bit, each cell in the first cell array comprising an inverter coupled in series with one impedance from a first impedance array and a compensation circuit coupled in parallel with the inverter and the one impedance from the first impedance array, the compensation circuit being configured to receive at least one bias signal and adjust the output of the at least one cell based on the at least one bias signal;
• and
• a second cell array comprising a second plurality of cells each being configured to receive a state of one bit from a second subset of the plurality of bits and provide an output based on the received state of the one bit, each cell in the second cell array comprising an inverter coupled in series with one impedance from a second impedance array;
• and
• an output coupled to the first and second cell arrays, the output being configured to provide the analog signal.