Non-geometric scaling current steering digital to analog converter
AssigneeGlobalfoundries Inc.
InventorsSher J. Fang, Sherif H. K. Embabi
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure include a digital-to-analog converter (DAC). The DAC includes an output node and a plurality of equal sized cell transistors. Each of the plurality of equal sized cell transistors represents a distinct bit, the distinct bits including a least significant bit (LSB). The plurality of equal sized cell transistors are connected to the output node. The DAC includes at least one control circuit configured to modify a back gate voltage of one of the equal sized cell transistors representing the LSB to adjust a current output.
Claims17
A digital-to-analog converter (DAC) comprising:
- an output node;
- a plurality of equal sized cell transistors, each of the plurality of equal sized cell transistors representing a distinct bit, the plurality of distinct bits including a least significant bit (LSB), the plurality of equal sized cell transistors connected to the output node;
- and
- at least one control circuit configured to modify a back gate voltage of one of the equal sized cell transistors representing the LSB to adjust a current, wherein the current for the distinct bit representing the LSB is a multiple of 0.5 of a current of a unit cell having no control circuit.
A digital-to-analog converter (DAC) comprising:
- a plurality of stages, each stage comprising an equal sized cell transistor, all but one of the equal sized cell transistors having being electrically connected to a backgate control circuit, each of the stages representing a distinct bit, the plurality of stages connected to an output node, wherein the distinct bits include a most significant bit (MSB) and a least significant bit (LSB) and the MSB is represented by the transistor having no backgate control circuit;
- and
- the backgate control circuit configured to modify a backgate voltage of one of the equal cell size transistors to adjust the current of the one of the stages.
A segmented digital-to-analog converter (DAC) comprising:
- M thermometer bits and N binary bits;
- a plurality of binary stages, N, each of the N binary stages comprising an equal sized cell transistor, at least one of the equal sized cell transistors being electrically connected to a backgate control circuit, each of the stages representing a distinct bit, the plurality of distinct bits including a least significant bit (LSB), the plurality of stages connected to an output node;
- the backgate control circuit configured to modify a backgate voltage of one of the equal cell size transistors to adjust the current of the one of the stages wherein the current for the distinct bit representing the LSB is a multiple of 0.5 of a current of an equal sized unit cell transistor having no backgate control circuit;
- and
- (2M−1) thermometer stages, each thermometer stage comprising a cell transistor, each of the (2M−1) thermometer stages connected to the output node.
Dependencies are inferred from the claim text.