US 9,871,529 B1 · Asynchronous SAR ADC with conversion speed control feedback loop

Abstract

Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

Claims20

Dependent claims

A system for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), comprising:

the asynchronous SAR ADC configured to receive an analog input signal and output a digital output signal, the SAR ADC configured to receive an external sampling clock for sampling the analog input signal and configured to generate an asynchronous internal timing related to conversion of the analog input signal;
a timing detector circuit coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC, the timing detector circuit configured to output a timing detector signal representing the internal timing of the SAR ADC, the timing detector signal being generated based on the one or more internal signals;
and
a regulator circuit coupled to the timing detector circuit to receive the timing detector signal, the regulator circuit also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC, the feedback signal being generated based on the timing detector signal to automatically regulate the internal timing of the SAR ADC to match a target timing.

1 more element

A system for feedback control of an interleaved asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), comprising:

the interleaved asynchronous SAR ADC having multiple sub-channels, each sub-channel having a respective internal timing related to conversion of an analog input signal to a digital output signal;
and
a plurality of timing detector circuits, each timing detector circuit being coupled to a respective sub-channel for detecting the internal timing of the respective sub-channel, each timing detector circuit configured to output a respective timing detector signal representing the internal timing of the respective sub-channel.

Dependencies are inferred from the claim text.

Asynchronous SAR ADC with conversion speed control feedback loop

Life of this patent

Asynchronous SAR ADC with conversion speed control feedback loop

Life of this patent

Abstract

Claims20