Back to results
US 9,871,523 B2Granted
High speed level translator
AssigneeInternational Business Machines Corporation
InventorJohn A. Fifield
Life of this patent
Estimating the term…
Abstract
A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.
Claims14
A level translator, comprising:
- a resistor divider configured to be switched on/off to provide an output of a low voltage and a high voltage;
- and
- a one-shot circuit coupled to the output and comprised of an inverter chain and a pull-up stack of transistors in parallel with the resistor divider coupled to receive an input signal oscillating between a voltage Vdd and a ground, the one-shot circuit conducting for a transition from a first state to a second state through a conduction path provided by the pull-up stack, and non-conducting for an opposite transition,
- wherein the one-shot circuit translates from the low voltage to the high voltage using the transistors arranged in parallel with a first resistor of the resistor divider and the inverter chain having outputs controlling gates of the transistors to generate an output signal oscillating between a voltage VPP2 and VPP to provide a conduction path between an output level of the first resistor for operation between voltage levels with which the Vdd and the ground can be translated to VPP2 and VPP.
1 more element
A level translator, comprising:
- a resistor divider comprising a first resistor R0 and a second resistor R1, in series, which is enabled by transistors T0 and T1, the transistor T1 is a series stack device to limit stress across transistor T0 to Vdd;
- and
- a one-shot circuit in parallel with the resistor divider and comprising a pull-up stack comprising two transistors T2 and T3, in series, which allows conduction from VPP to V2IN to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state,
- wherein
- resistive values of the resistors R0 and R1 are chosen to output voltage signal V2IN of approximately VPP2 when the transistor T0 receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V2IN is approximately VPP, and
- the pull-up stack is enabled during transition of low-to-high switching which increases switching speed and is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack.
3 more elements
Dependencies are inferred from the claim text.