Voting circuit and self-correcting latches

A circuit arrangement, comprising:

• a first voting circuit, the first voting circuit including:
• a pull-up circuit connected to a first output node and to a positive supply voltage,
• a pull-down circuit connected to the first output node and to ground,
• the pull-up circuit configured and arranged to pull the first output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and
• the pull-down circuit configured and arranged to pull the first output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state;
• a second voting circuit, the second voting circuit including:
• a pull-up circuit connected to a second output node and to the positive supply voltage,
• a pull-down circuit connected to the second output node and to ground,
• the pull-up circuit configured and arranged to pull the second output node to the positive supply voltage in response to complementary output signals from the first and third bi-stable circuits being in a first state, and
• the pull-down circuit configured and arranged to pull the second output node to ground in response to complementary output signals from the first and third bi-stable circuits being in a second state that is opposite the first state;
• and
• a third voting circuit, the third voting circuit including:
• a pull-up circuit connected to a third output node and to the positive supply voltage,
• a pull-down circuit connected to the third output node and to ground,
• the pull-up circuit configured and arranged to pull the third output node to the positive supply voltage in response to complementary output signals from the first and second bi-stable circuits being in a first state, and
• the pull-down circuit configured and arranged to pull the third output node to ground in response to complementary output signals from the first and second bi-stable circuits being in a second state that is opposite the first state wherein the first, second, and third output nodes are coupled together.

A circuit arrangement, comprising:

• a first bi-stable circuit;
• a second bi-stable circuit;
• a third bi-stable circuit;
• a first transistor of a first type serially connected to a second transistor of the first type, wherein the first transistor is serially coupled to a positive supply voltage;
• a third transistor of a second type serially connected to a fourth transistor of the second type, wherein the second transistor is serially connected to the third transistor at an output node, and the fourth transistor is serially coupled to ground;
• a transmission gate connected between the true output of the first bi-stable circuit and the output node;
• wherein:
• the output node is coupled to receive true output of the first bi-stable circuit;
• gates of the first and third transistors are coupled to receive complementary output of the second bi-stable circuit;
• gates of the second and fourth transistors coupled to receive complementary output of the third bi-stable circuit;
• and
• an output signal line connected to the output node, wherein a state of a signal on the output signal line is a state of a majority of true outputs of the first, second, and third bi-stable circuits.