On-die termination control without a dedicated pin in a multi-rank system
AssigneeIntel Corporation
InventorsKuljit S. Bains, Nadav Bonen, Christopher E. Cox, Alexey Kostinsky
Life of this patent
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Abstract
A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
Claims27
A dynamic random access memory (DRAM) device comprising:
- input/output interface hardware to receive a memory access command followed by a CAS-2 (column address selection) command;
- on-die termination (ODT) circuitry to selectively apply termination to a data signal line;
- and
- a register to store an ODT setting to indicate a termination impedance for non-target termination;
- wherein the DRAM device is to apply the termination impedance for non-target termination to the data signal line in response to receipt of a non-target CAS-2 command.
A method for termination in a dynamic random access memory (DRAM) device, comprising:
- receiving a memory access command followed by a CAS-2 (column address selection) command;
- determining from a register an on-die termination (ODT) setting that indicates a termination impedance for non-target termination;
- and
- selectively applying to a data signal line the non-target termination impedance with ODT circuitry in response to receiving a non-target CAS-2 command.
An apparatus for input/output termination, comprising:
- means for receiving a memory access command followed by a CAS-2 (column address selection command;
- means for determining from a register an on-die termination (ODT) setting that indicates a termination impedance for non-target termination;
- and
- means for selectively applying to a data signal line the non-target termination impedance with ODT circuitry in response to receiving a non-target CAS-2 command.
Dependencies are inferred from the claim text.