Memory interface circuit capable of controlling driving ability and associated control method
AssigneeMediatek Inc.
InventorsShang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
Life of this patent
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Abstract
A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
Claims31
A memory interface circuit, comprising:
- a first variable impedance circuit, coupled between a first supply voltage and a pad;
- and
- a second variable impedance circuit, coupled between a second supply voltage and the pad;
- wherein the memory interface circuit is applied to a dynamic random access memory (DRAM) controller or a DRAM module, and when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled by a digital control signal generated by the DRAM controller to have different setting in response to the changing of the first supply voltage.
A memory interface circuit, comprising:
- a programmable reference voltage generator, for generating a reference voltage according to a control signal generated according to a level of a supply voltage of the memory interface circuit;
- and
- a comparator, for comparing a received signal from a pad with the reference voltage to re-generate the received signal;
- wherein the memory interface circuit is applied in a DRAM module, and when the supply voltage changes, the programmable reference voltage generator receives another control signal from a DRAM controller to change a level of the reference voltage.
A control method of a memory interface circuit within a DRAM controller or a DRAM module, wherein the memory interface comprises a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad, and the control method comprises:
- when the first supply voltage changes, receiving a digital control signal generated by the DRAM controller to apply different setting to at least one of the first variable impedance circuit and the second variable impedance circuit of the memory interface circuit within the DRAM controller or the DRAM module in response to the changing of the first supply voltage.
A memory interface circuit within a dynamic random access memory (DRAM) controller or a DRAM module, comprising:
- a first variable impedance circuit, coupled between a first supply voltage and a pad;
- and
- a second variable impedance circuit, coupled between a second supply voltage and the pad;
- wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage;
- and the first variable impedance circuit or the second variable impedance circuit changes its impedance in response to the changing of the first supply voltage when a clock enable (CKE) signal is at a low voltage level.
A memory interface circuit within a dynamic random access memory (DRAM) controller or a DRAM module, comprising:
- a first variable impedance circuit, coupled between a first supply voltage and a pad;
- and
- a second variable impedance circuit, coupled between a second supply voltage and the pad;
- wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage;
- and the first variable impedance circuit or the second variable impedance circuit changes its impedance in response to the changing of the first supply voltage when no clock signal is transmitted via the memory interface circuit.
A memory interface circuit, comprising:
- a first variable impedance circuit, coupled between a first supply voltage and a pad;
- and
- a second variable impedance circuit, coupled between a second supply voltage and the pad;
- wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage;
- and the first variable impedance circuit or the second variable impedance circuit changes its impedance in response to the changing of the first supply voltage when no clock signal is transmitted via the memory interface circuit;
- wherein the memory interface circuit is applied in the DRAM module, and when the first supply voltage changes, the first variable impedance circuit and the second variable impedance circuit serve as an on-die termination, and the DRAM module re-applies a ZQ calibration.
Dependencies are inferred from the claim text.