Methods and apparatus for continuous current limiting for FETS in high inductive load systems

A method, comprising:

• receiving an enable signal;
• coupling a current conduction path of an FET between a supply voltage terminal and an output terminal for supplying current;
• coupling a voltage and a pull up bias current to a gate terminal of the FET;
• sensing current flowing through the FET;
• comparing the sensed current flowing through the FET to a predetermined current limit;
• reducing the current at the gate terminal of the FET, responsive to comparing the current flowing through the FET to the predetermined current limit;
• comparing a rate of increase of current flowing through the FET to a rate increase threshold;
• and
• reducing the pull up bias current to the gate terminal of the FET responsive to the comparing the rate of increase of current flowing through the FET.

An integrated circuit, comprising:

• a terminal for driving a gate of a power FET having a current conduction path coupled between a voltage supply and a load;
• a voltage input terminal for coupling a supply voltage to the integrated circuit;
• a pull up bias circuit coupled to the terminal for driving the gate of the power FET and to the voltage input terminal for coupling an increased power supply;
• a current sensing circuit coupled to the voltage input terminal to receive a voltage proportional to the current flowing in the power FET, and having a sensed current output;
• a current limit comparator comparing the sensed current to a current limit;
• a pull down current circuit coupled to the current limit comparator and to the terminal for driving the gate of the power FET;
• a current time derivative circuit coupled to the sensed current;
• and
• a current reduction circuit coupled to the current time derivative circuit and to the pull up bias circuit.