Semiconductor device, manufacturing method thereof, and electronic device

A semiconductor device comprising:

• a first insulating layer over a substrate;
• a first metal oxide layer over the first insulating layer;
• an oxide semiconductor layer over the first metal oxide layer;
• a second metal oxide layer over the first insulating layer and the oxide semiconductor layer;
• a first gate insulating layer over the second metal oxide layer;
• and
• a gate electrode layer over the first gate insulating layer,
• wherein the second metal oxide layer and the first gate insulating layer each comprise a region facing side surfaces of the first metal oxide layer and the oxide semiconductor layer,
• wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
• wherein the first region and the second region each comprise a region overlapping with the gate electrode layer,
• wherein the second region is between the first region and the third region,
• wherein the second region comprises a region with lower resistance than the first region,
• wherein the third region comprises a region with lower resistance than the second region,
• wherein the second region and the third region each comprise a region containing an element N, and
• wherein N is phosphorus, argon, or xenon.

A semiconductor device comprising:

• a first insulating layer over a substrate;
• a first metal oxide layer over the first insulating layer;
• an oxide semiconductor layer over the first metal oxide layer;
• a second metal oxide layer over the oxide semiconductor layer;
• a gate insulating layer over the second metal oxide layer;
• a second insulating layer over the second metal oxide layer;
• and
• a gate electrode layer over the gate insulating layer,
• wherein the gate insulating layer comprises a region in contact with a side surface of the gate electrode layer,
• wherein the second insulating layer comprises a region in contact with the gate insulating layer,
• wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
• wherein the first region comprises a region overlapping with the gate electrode layer,
• wherein the second region comprises a region overlapping with the gate insulating layer or the second insulating layer,
• wherein the second region is between the first region and the third region,
• wherein the second region and the third region each comprise a region containing an element N, and
• wherein N is phosphorus, argon, or xenon.