Thermally tuning strain in semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCarlos H. Diaz, Chih-Hao Wang, Gwan Sin Chang, Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
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Abstract
A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.
Claims20
A device comprising:
- a substrate;
- a silicon-containing oxide region over the substrate, with pores distributed in the silicon-containing oxide region;
- a silicon region overlying the silicon-containing oxide region;
- a first epitaxial region contacting a first sidewall of the silicon-containing oxide region and a first sidewall of the silicon region;
- a second epitaxial region contacting a second sidewall of the silicon-containing oxide region and a second sidewall of the silicon region, wherein the silicon-containing oxide region is disposed between the first epitaxial region and the second epitaxial region;
- a gate dielectric on a top surface and a sidewall of the silicon region;
- and
- a gate electrode over the gate dielectric.
A device comprising:
- a semiconductor substrate;
- an isolation region comprising a first portion and a second portion;
- a first source/drain region contacting the first portion of the isolation region, the first source/drain region having a crystalline structure and being doped with a first dopant;
- a second source/drain region contacting the second portion of the isolation region, the second source/drain region having a crystalline structure and being doped with the first dopant;
- a silicon oxide region comprising pores therein, the silicon oxide region comprising:
- a lower portion between the first source/drain region and the second source/drain region, wherein the lower portion is lower than a top surface of the isolation region;
- and
- an upper portion higher than the top surface of the isolation region, wherein the upper portion overlaps the lower portion;
- a silicon region overlapping the silicon oxide region;
- a gate dielectric comprising a first portion and a second portion on opposite sides of the upper portion of the silicon oxide region;
- and
- a gate electrode over the gate dielectric.
A device comprising:
- a semiconductor substrate;
- an isolation region comprising a first portion and a second portion;
- a silicon oxide region comprising pores therein;
- a silicon region overlapping the silicon oxide region;
- a first source/drain region comprising a first sidewall in contact with a first sidewall of the silicon oxide region and a first sidewall of the silicon region;
- a second source/drain region comprising a second sidewall in contact with a second sidewall of the silicon oxide region and a second sidewall the silicon region, wherein the silicon oxide region is disposed between the first source/drain region and the second source/drain region;
- a gate dielectric comprising portions on opposite sides of the silicon oxide region;
- and
- a gate electrode over the gate dielectric.
Dependencies are inferred from the claim text.