Dual strained nanosheet CMOS and methods for fabricating

A method, comprising:

• disposing a strained relaxed buffer layer on a handle substrate;
• epitaxially forming alternating sheets of tensile strained silicon and relaxed silicon-germanium on the strained relaxed buffer layer to form a lattice;
• disposing an isolation structure on the epitaxially formed sheets to isolate a first portion of the lattice from a second portion of the lattice;
• disposing a first dummy gate and spacers on an upper sheet of the first portion of the lattice and a second dummy gate and spacers on an upper sheet of the second portion of the lattice;
• forming source regions and drain regions on the first portion of the lattice adjacent the first dummy gate and spacers and on the second portion of the lattice adjacent the second dummy gate and spacers;
• depositing an interlayer dielectric on an upper surface of the formed source regions and drain regions;
• masking the first portion of the lattice;
• removing the second dummy gate;
• selectively removing portions of the relaxed silicon-germanium sheets under a second location from which the second dummy gate was removed thereby forming voids above and below the remaining tensile strained silicon sheets;
• removing the mask from the masked first portion of the lattice;
• masking the second portion of the lattice;
• removing the first dummy gate;
• selectively removing portions of the tensile strained silicon from under a first location from which the first dummy gate was removed thereby forming voids above and below the remaining silicon germanium sheets;
• performing a low temperature condensation process to increase a germanium content in the relaxed silicon-germanium layers in the first portion of the lattice relative to the second portion of the lattice, wherein performing the low temperature condensation process reduces a thickness of the silicon-germanium layers in the first portion substantially to a thickness of the silicon sheets in the second portion;
• and
• filling the voids above and below the remaining tensile strained silicon sheets under the second location and above and below the remaining relaxed silicon germanium sheets under the first location with a high k dielectric/metal gate material.

An apparatus, comprising:

• a substrate having a strained relaxed buffer layer;
• a PFET structure on the strained relaxed buffer layer, the PFET structure comprising,
• a PFET gate comprising a high k dielectric/metal gate material,
• alternating nanosheets of relaxed silicon-germanium and the high k dielectric/metal gate material under the PFET gate, and
• source and drain regions disposed adjacent the alternating nanosheets of relaxed silicon-germanium and the high k dielectric/metal gate material;
• an NFET structure on the strained relaxed buffer, the NFET structure comprising,
• an NFET gate comprising the high k dielectric/metal gate material,
• alternating nanosheets of tensile strained silicon and the high k dielectric/metal gate material under the NFET gate, and
• source and drain regions disposed adjacent the alternating nanosheets of tensile strained silicon and the high k dielectric/metal gate material;
• and
• an isolation structure separating the PFET structure and the NFET structure.