Method for forming semiconductor device structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
Life of this patent
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Abstract
The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.
Claims20
A semiconductor device structure, comprising:
- a gate stack structure formed on a substrate;
- gate spacers formed on sidewalls of the gate stack structure;
- an isolation structure formed in the substrate;
- a source/drain stressor structure formed between the gate stack structure and the isolation structure;
- and
- a metal silicide layer formed on the source/drain stressor structure, wherein the metal silicide layer has a horizontal portion and a sloped portion, a portion of the sloped portion of the metal silicide layer is below a top surface of the isolation structure, the horizontal portion is parallel to a top surface of the substrate and is in direct contact with the gate spacers.
A semiconductor device structure, comprising:
- a gate stack structure formed on a substrate;
- an isolation structure formed in the substrate;
- a stressor layer formed between the gate stack structure and the isolation structure, wherein the stressor layer has a first facet parallel to a top surface of the isolation structure and a second facet connected to the first facet, wherein the second facet is slanted downward from the first facet to a sidewall of the isolation structure;
- a recess formed between the second facet and the stressor layer and the isolation structure;
- a dielectric layer formed in the recess, wherein a portion of the dielectric layer is below a top surface of the isolation structure;
- a metal silicide layer formed over the stressor layer;
- and
- a contact structure formed on the metal silicide layer, wherein the contact structure is electrically connected to the metal silicide layer.
A semiconductor device structure, comprising:
- a gate stack structure formed on a wafer;
- a first gate spacer and a second gate spacer formed on opposite sidewalls of the gate stack structure;
- an isolation structure formed in the wafer;
- a first source/drain stressor structure formed adjacent to the first gate spacer, wherein the first source/drain stressor structure comprises a first capping layer;
- a second source/drain stressor structure formed adjacent to the second gate spacer, wherein the second source/drain stressor structure comprises a second capping layer, and a top surface of the second capping layer is higher than a top surface the first capping layer;
- and
- a metal silicide layer formed on the first source/drain stressor structure, wherein a top surface of the metal silicide layer is level with the top surface of the second capping layer.
Dependencies are inferred from the claim text.