Semiconductor device
AssigneeUnited Microelectronics Corp.
InventorsShih-Cheng Chen, Tsai-Yu Wen, Shan Ye, Tsuo-Wen Lu
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Abstract
A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.
Claims17
A semiconductor device comprising:
- a substrate;
- an electrode layer disposed on the substrate;
- and
- a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
- a ferroelectric (FE) layer disposed on the substrate;
- an anti-ferroelectric (AFE) layer sandwiched between the ferroelectric layer and the substrate, the FE layer and the AFE layer comprising different materials, wherein the AFE layer comprises a material selected from the group consisting of lead indium niobate (Pb(InNb)O3), niobium-sodium oxide (NbNaO3), lead zirconate (ZrPbO3), lead lanthanum zirconate titanate (TiZrLaPbO2), lead zirconate titanate (TiZrPbO3), ammonium dihydrogen phosphate (NH4H2PO4, ADP), and ammonium dihydrogen arsenate (NH4H2AsO4, ADA);
- and
- a mid-gap metal layer sandwiched between the ferroelectric layer and the AFE layer.
A semiconductor device comprising:
- a substrate;
- an electrode layer disposed on the substrate;
- and
- a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
- an amorphous ferroelectric (FE) dielectric layer;
- a mid-gap metal layer disposed between the amorphous ferroelectric dielectric layer and the substrate, the mid-gap metal layer directly contacting the amorphous ferroelectric dielectric layer;
- and
- a polycrystalline dielectric layer,
- wherein the amorphous ferroelectric dielectric layer and the polycrystalline dielectric layer both comprise hafnium oxide materials.
A semiconductor device comprising:
- a substrate;
- an electrode layer disposed on the substrate;
- and
- a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
- a ferroelectric (FE) layer disposed on the substrate, wherein the ferroelectric layer comprises a material selected from the group consisting of lead zirconate titanate (PbZrTiO3, PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O3, PLZT), strontium bismuth tantalate (SrBiTa2O9, SBT), bismuth lanthanum titanate ((BiLa)4Ti3O12, BLT), and barium strontium titanate (BaSrTiO3, BST);
- an anti-ferroelectric (AFE) layer sandwiched between the ferroelectric layer and the substrate, the FE layer and the AFE layer comprising different materials;
- and
- a mid-gap metal layer sandwiched between the ferroelectric layer and the AFE layer.
Dependencies are inferred from the claim text.