Lateral DMOS device with dummy gate

A device comprising:

• a first drain/source region and a second drain/source region over a substrate;
• a first gate over a first dielectric layer;
• and
• a second gate over a second dielectric layer, wherein:
• a thickness of the second dielectric layer is greater than a thickness of the first dielectric layer;
• the first dielectric layer and the second dielectric layer form a step;
• the first dielectric layer extends from an edge of the first drain/source region to the step;
• the second dielectric layer extends from the step to an edge of the second drain/source region;
• and
• the step is free of a gate material thereon.

A transistor comprising:

• an extended drift region over a substrate;
• a drain region in the extended drift region;
• a channel region in the extended drift region;
• a source region in the channel region;
• a first dielectric layer with a first thickness formed over the extended drift region;
• a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein:
• the first thickness is greater than the second thickness;
• at least one portion of the first dielectric layer is below a top surface of the extended drift region;
• and
• a boundary between the first dielectric layer and the second dielectric layer is free of a gate material thereon;
• a first gate on the first dielectric layer;
• and
• a second gate on the second dielectric layer.