Back to results
US 9,871,132 B1Granted
Extended drain metal-oxide-semiconductor transistor
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsKun Liu, Xiaoping Wang, Francis Lionel Benistant, Li Cao
Life of this patent
Estimating the term…
Abstract
Devices and methods for forming a device are disclosed. A transistor is formed on the substrate. The transistor includes a gate, a source and a drain. An insulation layer is formed on the substrate. The insulation layer is partially disposed on the gate and a sidewall of the gate. The drain is offset from the gate by the insulation layer. An overlayer is formed on the substrate covering the transistor and insulation layer. A field plate in the form of a field plate contact is formed in the overlayer. The field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.
Claims19
A method for forming a device comprising:
- providing a substrate, wherein the substrate comprises a medium voltage (MV) device region, wherein the MV device region comprises
- first, second, and third wells,
- wherein the second and third wells are disposed in the first well, the second and third wells are distinct wells,
- wherein the first well is lightly doped with first polarity type dopants, the second well is intermediately doped with second polarity type dopants and the third well is intermediately doped with first polarity type dopants, and
- wherein the first well is a deep well, the second doped well is a body well, and the third doped well is a drift well;
- forming a first polarity type transistor on the substrate in the MV device region, wherein the transistor comprises a gate, a source and a drain;
- forming an insulation layer on the substrate, wherein the insulation layer is partially disposed on the gate and a sidewall of the gate, and wherein the drain is offset from the gate by the insulation layer;
- forming an overlayer on the substrate covering the transistor and insulation layer;
- and
- forming a field plate in the form of a field plate contact in the overlayer, wherein the field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.
7 more elements
A method for forming a device comprising:
- providing a substrate, wherein the substrate comprises a medium voltage (MV) device region, wherein the MV device region comprises
- first, second, and third wells,
- wherein the second and third wells are disposed in the first well, the second and third wells are distinct wells,
- wherein the first well is lightly doped with first polarity type dopants, the second well is intermediately doped with second polarity type dopants and the third well is intermediately doped with first polarity type dopants, and
- wherein the first well is a deep well, the second doped well is a body well, and the third doped well is a drift well;
- forming a transistor on the substrate in the MV device region, wherein the transistor comprises a gate;
- forming an insulation layer on the substrate, wherein the insulation layer is partially disposed on the gate and a sidewall of the gate;
- forming an etch stop layer on the substrate, wherein the etch stop layer covers the transistor;
- forming a dielectric layer over the etch stop layer;
- and
- forming a field plate in the form of a field plate contact in the etch stop layer and dielectric layer, wherein the field plate contact is disposed on and coupled to the insulation layer.
8 more elements
A device comprising:
- a substrate, wherein the substrate comprises a medium voltage (MV) device region, wherein the MV device region comprises
- first, second, and third wells,
- wherein the second and third wells are disposed in the first well, the second and third wells are distinct wells;
- wherein the first well is lightly doped with first polarity type dopants, the second well is intermediately doped with second polarity type dopants and the third well is intermediately doped with first polarity type dopants, and
- wherein the first well is a deep well, the second doped well is a body well, and the third doped well is a drift well;
- and
- a transistor disposed on the substrate in the MV device region, wherein the transistor comprises a gate, a source and a drain;
- an insulation layer disposed on the substrate, wherein the insulation layer is partially disposed on the gate and a sidewall of the gate, and wherein the drain is offset from the gate by the insulation layer;
- an overlayer disposed on the substrate covering the transistor and insulation layer;
- and
- a field plate in the form of a field plate contact disposed in the overlayer, wherein the field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.
8 more elements
Dependencies are inferred from the claim text.