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US 9,871,119 B2Granted
Method of manufacturing a termination arrangement for a vertical MOSFET
AssigneeInfineon Technologies Austria AG
InventorsAndrew Wood, Markus Zundel
Life of this patent
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Abstract
Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.
Claims21
A method comprising:
- arranging a semiconductor layer of a transistor structure, the semiconductor layer having an active region and an adjacent termination region, the termination region including a recessed area;
- forming a field insulator layer at a first portion of the recessed area of the termination region to form an insulator step structure at the bottom of the recessed area;
- and
- forming a gate insulator layer at a second adjacent portion of the recessed area of the termination region, the gate insulator layer adjoining the insulating step structure at the bottom of the recessed area.
1 more element
A method comprising:
- arranging a semiconductor layer of a transistor structure, the semiconductor layer having an active region and an adjacent termination region, the termination region including a recessed area;
- forming a field insulator layer at a first portion of the recessed area of the termination region to form an insulator step structure at the bottom of the recessed area, the step insulator structure being formed as a thickening of the field insulator layer from a first thickness to a second thickness;
- and
- forming a gate insulator layer at a second adjacent portion of the recessed area of the termination region, the gate insulator layer adjoining the insulating step structure at the bottom of the recessed area.
1 more element
Dependencies are inferred from the claim text.