Vertical transistor devices for embedded memory and logic technologies
AssigneeIntel Corporation
InventorsBrian S. Doyle, Uday Shah, Roza Kotlyar, Charles C. Kuo
Life of this patent
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Abstract
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.
Claims18
A method of fabricating a vertical transistor device, comprising:
- depositing an epitaxial source semiconductor layer on a substrate;
- depositing an epitaxial channel semiconductor layer on the source semiconductor layer;
- depositing an epitaxial drain semiconductor layer on the channel semiconductor layer;
- etching through the drain, channel, and source semiconductor layers to form a drain semiconductor region, a channel semiconductor region, and a source semiconductor region, each having a plurality of sidewalls;
- and
- forming a gate electrode region to surround the plurality of sidewalls of the channel semiconductor region, wherein a composition of at least one of the semiconductor regions varies along a longitudinal axis of the vertical transistor device that is perpendicular with respect to a surface of the substrate, wherein the source semiconductor region has a higher effective mass than that of the channel and drain semiconductor regions.
A method of fabricating a vertical transistor device, comprising:
- depositing an epitaxial source semiconductor region on a substrate;
- depositing an epitaxial channel semiconductor region on the source semiconductor region;
- depositing an epitaxial drain semiconductor region on the channel semiconductor region;
- forming a plurality of sidewalls through each of the drain, channel, and source semiconductor regions;
- and
- forming a gate electrode region to surround a plurality of sidewalls of the channel semiconductor region, wherein a composition of the gate electrode region varies along a longitudinal axis of the vertical transistor device that is perpendicular with respect to a surface of the substrate.
A method of fabricating a vertical transistor device having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the method comprising:
- depositing a source semiconductor region on the crystalline substrate;
- depositing a channel semiconductor region on the source semiconductor region;
- depositing a drain semiconductor region on the channel semiconductor region;
- etching through the drain, channel, and source semiconductor regions to form a plurality of sidewalls through the drain, channel, and source semiconductor regions;
- and
- forming a gate dielectric region and a gate electrode region to surround a plurality of channel semiconductor region sidewalls of the vertical transistor device, wherein the depositing further comprises modifying growth conditions to vary the semiconductor composition across a thickness of the channel semiconductor region.
Dependencies are inferred from the claim text.