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US 9,871,111 B2Granted
Semiconductor device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Ta Hsieh, Tetsu Ohtou, Ching-Wei Tsai, Chih-Hao Wang
Life of this patent
Estimating the term…
Abstract
A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel region within the nanowire. In additional embodiments multiple nanowires, multiple bottom contacts, multiple top contacts, and multiple gate contacts are utilized.
Claims20
A semiconductor device comprising:
- a first nanowire over a semiconductor substrate, the first nanowire being perpendicular to and in physical contact with the semiconductor substrate and comprising a first source/drain region, a channel region over the first source/drain region, and a second source/drain region over the channel region;
- a first contact pad on the semiconductor substrate and at least partially surrounding the first source/drain region and covering at least a portion of a sidewall of the first nanowire;
- a gate electrode at least partially surrounding the channel region;
- a second contact pad in physical connection with a semiconductor section of the second source/drain region, wherein the second contact pad has a surface facing the semiconductor substrate, wherein the surface is planar from a first end of the second contact pad to a second end of the second contact pad opposite the first end and wherein the surface remains planar as the surface extends over the first nanowire;
- and
- a first bottom contact in electrical connection with the first contact pad, wherein the first bottom contact is a U-shaped contact.
3 more elements
A semiconductor device comprising:
- a first contact pad on a semiconductor substrate;
- a second contact pad directly over the first contact pad, wherein the second contact pad has a first surface that is planar from a first end of the second contact pad to a second end of the second contact pad opposite the first end, wherein the first surface faces the semiconductor substrate;
- a first nanowire extending between the first contact pad and the first surface of the second contact pad and in physical contact with the semiconductor substrate, wherein the first surface is in physical contact with a semiconductor material of the first nanowire and remains planar as it extends over the first nanowire;
- a gate electrode surrounding a channel region of the first nanowire;
- and
- a contact in physical contact with the first contact pad, wherein the contact has either an “L” shape or a “U” shape.
3 more elements
A method of manufacturing a semiconductor device, the method comprising:
- forming a first nanowire from a substrate;
- depositing a first contact pad adjacent to a lower portion of the first nanowire after the forming the first nanowire;
- forming a gate electrode adjacent to a middle portion of the first nanowire;
- forming a dielectric layer at least partially over the gate electrode and the first nanowire after the forming the gate electrode and after forming the first nanowire;
- planarizing the dielectric layer to form a planar surface between the dielectric layer and the first nanowire;
- forming a second contact pad adjacent to an upper portion of the first nanowire and in physical contact with the planar surface;
- and
- forming a first contact to the first contact pad, wherein the first contact is an L-shaped contact.
5 more elements
Dependencies are inferred from the claim text.