Heterogeneous pocket for tunneling field effect transistors (TFETs)

A system comprising:

• a processor;
• and
• a memory communicatively coupled to the processor;
• wherein at least one of the processor or the memory includes at least one tunneling field effect transistor (TFET) comprising:
• a drain region;
• a source region having a conductivity type opposite of the drain region;
• a channel region disposed between the source region and the drain region, the channel region comprising a semiconductor material the same as the source region;
• a gate disposed over the channel region;
• and
• a heterogeneous pocket disposed near a junction of the source region and the channel region, wherein the heterogeneous pocket comprises a semiconductor material different than the channel region, and wherein the heterogeneous pocket comprises a tunneling barrier less than a bandgap of the channel region to form a quantum well in the channel to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage, wherein the channel region of the TFET comprises a semiconductor material including indium, and the heterogeneous pocket comprises a semiconductor material having a higher percentage of indium.

A tunneling field effect transistor (TFET) comprising:

• a drain region;
• a source region having a conductivity type opposite of the drain region;
• a channel region disposed between the source region and the drain region;
• a gate disposed over the channel region;
• and
• a heterogeneous pocket disposed near a junction of the source region and the channel region, wherein the heterogeneous pocket comprises a semiconductor material different than the channel region and wherein the heterogeneous pocket comprises a lower tunneling barrier than a bandgap of the channel region to form a quantum well to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage, and wherein the channel region comprises a semiconductor material including indium, and the heterogeneous pocket comprises a semiconductor material having a higher percentage of indium.

A tunneling field effect transistor (TFET) comprising:

• a drain region;
• a source region having a conductivity type opposite of the drain region;
• a channel region disposed between the source region and the drain region;
• a gate disposed over the channel region;
• and
• a heterogeneous pocket disposed near a junction of the source region and the channel region, wherein the heterogeneous pocket comprises a semiconductor material different than the channel region, and wherein the heterogeneous pocket comprises a lower tunneling barrier than a bandgap of the channel region to form a quantum well to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage and wherein a valence band of the source region is aligned with discrete energy levels of the heterogeneous pocket.

A system comprising:

• a processor;
• and
• a memory communicatively coupled to the processor;
• wherein at least one of the processor or the memory includes at least one tunneling field effect transistor (TFET) comprising:
• a drain region;
• a source region having a conductivity type opposite of the drain region;
• a channel region disposed between the source region and the drain region;
• a gate disposed over the channel region;
• and
• a heterogeneous pocket disposed near a junction of the source region and the channel region, wherein the heterogeneous pocket comprises a semiconductor material different than the channel region, and wherein the heterogeneous pocket comprises a tunneling barrier less than a bandgap of the channel region to form a quantum well in the channel to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage and wherein the channel region of the TFET comprises a semiconductor material including indium, and the heterogeneous pocket comprises a semiconductor material having a higher percentage of indium.

A system comprising:

• a processor;
• and
• a memory communicatively coupled to the processor;
• wherein at least one of the processor or the memory includes at least one tunneling field effect transistor (TFET) comprising:
• a drain region;
• a source region having a conductivity type opposite of the drain region;
• a channel region disposed between the source region and the drain region;
• a gate disposed over the channel region;
• and
• a heterogeneous pocket disposed near a junction of the source region and the channel region, wherein the heterogeneous pocket comprises a semiconductor material different than the channel region, and wherein the heterogeneous pocket comprises a tunneling barrier less than a bandgap of the channel region to form a quantum well in the channel to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage and wherein a valence band of the source region of the TFET is aligned with discrete energy levels of the heterogeneous pocket.