Nanowire semiconductor device structure and method of manufacturing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGerben Doornbos, Mark van Dal
Life of this patent
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Abstract
A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a nanowire over a substrate, wherein the nanowire comprises a channel;
- implanting a first dopant into the nanowire to form a source and a drain in the nanowire, the channel disposed between the source and the drain, wherein the source has a first conductivity type and the drain has the first conductivity type;
- covering a portion of the drain;
- and
- implanting a first minority carrier lifetime reducing dopant into the source after the covering the portion of the drain, the first minority carrier lifetime reducing dopant different from the first dopant, wherein the first minority carrier lifetime reducing dopant is substantially confined to the source, and wherein the channel is substantially free of the first minority carrier lifetime reducing dopant.
A method of manufacturing a semiconductor device, the method comprising:
- forming a source region, a drain region, and a channel region within a nanowire, wherein the source region has a first conductivity type and the drain region has the first conductivity type;
- forming a first spacer on the nanowire, the first spacer covering a portion of the source region;
- forming a second spacer on the nanowire, the second spacer covering a portion of the drain region;
- and
- modifying the source region and the drain region to reduce a minority carrier lifetime within the source region and the drain region using a first modification process, wherein the source region and the drain region are part of a MOSFET, and wherein parameters of the first modification process are chosen to avoid modifying portions of the channel region adjacent the source region and portions of the drain region under the second spacer.
A semiconductor device comprising:
- a nanowire with a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region has a first conductivity type and the drain region has the first conductivity type, wherein the channel region is part of a MOSFET;
- and
- first dopants within and throughout the source region, wherein the first dopants are minority carrier lifetime reducing dopants and have a different concentration within the source region than within the drain region, wherein the junction between the source region and the channel region is substantially free of the first dopants, wherein the first dopants are one of nickel, cobalt, titanium, tantalum, oxygen, magnesium, or iron.
Dependencies are inferred from the claim text.