Nanosheet isolation for bulk CMOS non-planar devices

A semiconductor structure comprising:

• a semiconductor substrate including a first device region and a second device region, wherein first trench isolation structures surround said first and second device regions and extend below first and second pedestal portions of said semiconductor substrate;
• a first semiconductor material fin stack located above said first pedestal portion of said semiconductor substrate;
• a second semiconductor material fin stack located above said second pedestal portion of said semiconductor substrate;
• and
• second trench isolation structures located at ends of each first semiconductor material fin stack and said second semiconductor material fin stack, wherein a portion of one of said second trench isolation structures is located directly between a bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and another of said second trench isolation structures is located directly between a bottommost surface of said second semiconductor material fin stack and said second pedestal portion of said semiconductor substrate, and wherein said portion of said one of said second trench isolation structures that is located directly between said bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and said portion of said another of said second trench isolation structures directly between said bottommost surface of said second semiconductor material fin stack contacts a sidewall surface of one of said first trench isolation structures.