Memory arrays and methods of forming memory arrays

A method of forming a memory array, comprising:

• forming a first memory cell;
• forming a second memory cell directly adjacent to the first memory cell along a lateral direction, and vertically offset relative to the first memory cell;
• forming first and second wordlines over a substrate, the first and second wordlines being at a common elevation with each other, with the first memory cell being disposed over the first wordline and the second memory cell being disposed over the second wordline;
• and
• forming a bitline extending across the first and second memory cells and being electrically coupled to the first and second memory cells;
• the first memory cell being in a first vertical stack having a conductive extension material between the first memory cell and the bitline;
• the second memory cell being in a second vertical stack lacking a conductive extension between the second memory cell and the bitline, the second vertical stack comprising a first electrode material over and spaced from the second wordline, a programmable material over the first electrode material and an upper electrode material over the programmable material and in physical contact with the bitline.

A method of forming a memory array, comprising:

• forming a series of data/sense lines extending along a first direction;
• forming a series of access lines extending along a second direction which intersects the first direction;
• forming memory cells vertically between the access lines and the data/sense lines, the memory cells being arranged in a grid having columns along the first direction and rows along the second direction, the memory cells each having a vertical stack comprising a first electrode material separated from a second electrode material by intervening materials comprising a programmable material and a select device material;
• and
• wherein the memory cells in a common column as one another are formed in two alternating sets along the first direction;
• with the sets being a first set having memory cells at a first height and a second set having memory cells at a second height which is vertically offset relative to the first height, the second set having the first electrode material in direct physical contact with a single one of the data/sense lines and having the second electrode material spaced from an overlying access line, and the first set having the first electrode material spaced from a second one of the data/sense lines and the second electrode material in direct physical contact with the overlying access line.