Domain wall magnetic memory

A method for forming a memory cell comprising:

• providing a substrate with a cell region;
• forming a selector unit in the cell region, wherein the selector unit includes first and second bipolar junction transistors (BJTs), the first and second BJTs each comprises first, second and third BJT terminals, wherein
• the second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal,
• the third BJT terminal of the first BJT serves as a first bitline terminal, and
• the third BJT terminal of the second BJT serves as a second bitline terminal;
• and
• forming a storage unit over the selector unit, wherein the storage unit comprises
• a first pinning layer, the first pinning layer is coupled to the first BJT terminal of the first BJT,
• a second pinning layer, the second pinning layer is coupled to the first BJT terminal of the second BJT, and
• a free layer, the free layer includes an elongated member with first and second major surfaces and first and second end regions separated by a free region, wherein
• the first pinning layer is coupled to the second major surface of the free layer in the first end region,
• the second pinning layer is coupled to the second major surface of the free layer in the second end region, and
• a reference stack is disposed on the first major surface of the free layer in the free region, wherein the reference stack serves as a read bitline terminal.

A memory cell comprising:

• a substrate with a cell region;
• a selector unit in the cell region, wherein the selector unit includes first and second bipolar junction transistors (BJTs), wherein the first and second BJTs each comprises first, second and third BJT terminals;
• and
• a storage unit disposed over the selector unit, the storage unit comprises
• a first pinning layer, the first pinning layer is coupled to the first BJT terminal of the first BJT,
• a second pinning layer, the second pinning layer is coupled to the first BJT terminal of the second BJT, and
• a free layer disposed over the first and second pinning layers, the free layer includes an elongated member with first and second major surfaces and first and second end regions separated by a free region, wherein the first pinning layer is coupled to the second major surface of the free layer in the first end region, the second pinning layer is coupled to the second major surface of the free layer in the second end region.

A memory cell comprising:

• a substrate with a cell region;
• a selector unit in the cell region, wherein the selector unit includes first and second bipolar junction transistors (BJTs), the first and second BJTs each comprises first, second and third BJT terminals, wherein
• the second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal,
• the third BJT terminal of the first BJT serves as a first bitline terminal, and
• the third BJT terminal of the second BJT serves as a second bitline terminal;
• and
• a storage unit disposed over the selector unit, wherein the storage unit comprises
• a first pinning layer, the first pinning layer is coupled to the first BJT terminal of the first BJT,
• a second pinning layer, the second pinning layer is coupled to the first BJT terminal of the second BJT, and
• a free layer disposed over the pinning layers, the free layer includes an elongated member with first and second major surfaces and first and second end regions separated by a free region, wherein
• the first pinning layer is coupled to the second major surface of the free layer in the first end region,
• the second pinning layer is coupled to the second major surface of the free layer in the second end region, and
• a reference stack disposed on the first major surface of the free layer in the free region, wherein the reference stack serves as a read bitline terminal.